chapter 3 features of architecture and memory map 27 user s manual u10201ej2v4um00 3.1.2 addressing mode of data memory the 75xl architecture employed for the pd753036 provides the seven types of addressing modes as shown in table 3-1. this means that the data memory space can be efficiently addressed by the bit length of the data to be processed and that programming can be carried out efficiently. (1) 1-bit direct addressing (mem.bit) this mode is used to directly address each bit of the entire data memory space by using the operand of an instruction. the memory bank (mb) to be specified is fixed to 0 in the mode of mbe = 0 if the address specified by the operand ranges from 00h to 7fh, and to 15 if the address specified by the operand is 80h to ffh. in the mode of mbe = 0, therefore, both the data area of addresses 000h through 07fh and the peripheral hardware area of f80h through fffh can be addressed. in the mode of mbe = 1, mb = mbs; therefore, the entire data memory space can be addressed. this addressing mode can be used with four instructions: bit set and the two reset (set1 and clr1) instructions, and the two bit test instructions (skt and skf). example to set flag1, reset flag2, and test whether flag3 is 0 flag1 equ 03fh.1 ; bit 1 of address 3fh flag2 equ 087h.2 ; bit 2 of address 87h flag3 equ 0a7h.0 ; bit 0 of address a7h set1 mbe ; mbe 1 sel mb0 ; mbs 0 set1 flag1 ; flag1 1 clr1 flag2 ; flag2 0 skf flag3 ; flag3 = 0?
chapter 3 features of architecture and memory map 28 user s manual u10201ej2v4um00 fig. 3-2 configuration of data memory and addressing ranges of respective addressing modes remark : don t care 000h 01fh addressing mode memory bank enable flag general- purpose register area mem mem. bit @hl @h+mem. bit @de @dl stack address- ing fmem. bit pmem. @l mbe =0 mbe =1 mbe =0 mbe =1 data area static ram (memory bank 0) 07fh 0ffh 100h 1ebh 1ech 1ffh 200h 2ffh f80h fb0h fbfh fc0h ff0h fffh mbs =0 sbs =0 mbs =1 mbs =1 sbs =1 mbs =2 mbs =2 sbs =2 mbs =15 mbs =15 data area static ram (memory bank 1) display data memory data area static ram (memory bank 2) not provided peripheral hardware memory (memory bank 15) mbs =0
chapter 3 features of architecture and memory map 29 user s manual u10201ej2v4um00 table 3-1 addressing modes addressing mode representation specified address 1-bit direct addressing mem.bit bit specified by bit of address specified by mb and mem when mbe = 0 when mem = 00h-7fh : mb = 0 when mem = 80h-ffh : mb = 15 when mbe = 1 : mb = mbs 4-bit direct addressing mem address specified by mb and mem. when mbe = 0 when mem = 00h-7fh : mb = 0 when mem = 80h-ffh : mb = 15 when mbe = 1 : mb = mbs 8-bit direct addressing address specified by mb and mem (mem is even address) when mbe = 0 when mem = 00h-7fh : mb = 0 when mem = 80h-ffh : mb = 15 when mbe = 1 : mb = mbs 4-bit register indirect @hl address specified by mb and hl. addressing where, mb = mbe . mbs @hl+ address specified by mb and hl. however, mb = mbe . mbs. @hl hl+ automatically increments l register after addressing. hl automatically decrements l register after addressing. @de address specified by de in memory bank 0 @dl address specified by dl in memory bank 0 8-bit register indirect @hl address specified by mb and hl (contents of l register are even addressing number) where, mb = mbe . mbs bit manipulation fmem.bit bit specified by bit at address specified by fmem addressing fmem = fb0h-fbfh (interrupt-related hardware) ff0h-fffh (i/o port) pmem.@l bit specified by lower 2 bits of l register at address specified by higher 10 bits of pmem and lower 2 bits of l register. where, pmem = fc0h-fffh @h+mem.bit bit specified by bit at address specified by mb, h, and lower 4 bits of mem. where, mb = mbe . mbs stack addressing address specified by sp in memory bank 0 to 2 selected by sbs
chapter 3 features of architecture and memory map 30 user s manual u10201ej2v4um00 (2) 4-bit direct addressing (mem) this addressing mode is used to directly address the entire memory space in 4-bit units by using the operand of an instruction. like the 1-bit direct addressing mode, the area that can be addressed is fixed to the data area of addresses 000h through 07fh and the peripheral hardware area of f80h through fffh in the mode of mbe = 0. in the mode of mbe = 1, mb = mbs, and the entire data memory space can be addressed. this addressing mode is applicable to the mov, xch, incs, in, and out instructions. caution if data related to i/o ports is stored to the static ram in bank 1 as shown in example 1 below, the program efficiency is degraded. to program without changing mbs as shown in example 2, store the data related to i/o ports to the addresses 00h through 7fh of bank 0. examples 1. to output data of buff to port 5 buff equ 11ah ; buff is at address 11ah set1 mbe ; mbe 1 sel mb1 ; mbs 1 mov a, buff ; a (buff) sel mb15 ; mbs 15 out port5, a ; port5 a 2. to input data from port 4 and store it to data1 data1 equ 5fh ; stores data1 to address 5fh clr1 mbe ; mbe 0 in a, port4 ; a port4 mov data1, a ; (data1) a (3) 8-bit direct addressing (mem) this addressing mode is used to directly address the entire data memory space in 8-bit units by using the operand of an instruction. the address that can be specified by the operand is an even address. the 4-bit data of the address specified by the operand and the 4-bit data of the the address higher than the specified address are used in pairs and processed in 8-bit units by the 8-bit accumulator (xa register pair). the memory bank that is addressed is the same as that addressed in the 4-bit direct addressing mode. this addressing mode is applicable to the mov, xch, in, and out instructions. examples 1. to transfer the 8-bit data of ports 4 and 5 to addresses 20h and 21h data equ 020h clr1 mbe ; mbe 0 in xa, port4 ; x port 5, a port 4 mov data, xa ; (21h) x, (20h) a 2. to load the 8-bit data input to the shift register (sio) of the serial interface and, at the same time, set transfer data to instruct the start of transfer sel mb15 ; mbs 15 xch xa, sio ; xa ? (sio)
chapter 3 features of architecture and memory map 31 user s manual u10201ej2v4um00 (4) 4-bit register indirect addressing (@rpa) this addressing mode is used to indirectly address the data memory space in 4-bit units by using a data pointer (a pair of general-purpose registers) specified by the operand of an instruction. as the data pointer, three register pairs can be specified: hl that can address the entire data memory space by using mbe and mbs, and de and dl that always address memory bank 0, regardless of the specification by mbe and mbs. the user selects a register pair depending on the data memory bank to be used in order to carry out programming efficiently. example to transfer data 50h through 57h to addresses 110h through 117h data1 equ 57h data2 equ 117h set1 mbe sel mb1 mov d, #data1 shr4 mov hl, #data2 and 0ffh ; hl 17h loop : mov a, @dl ; a (dl) xch a, @hl ; a (hl) decs l ; l l 1 br loop the addressing mode that uses register pair hl as the data pointer is widely used to transfer, operate, compare, and input/output data. the addressing mode using register pair de or dl is used with the mov and xch instructions. by using this addressing mode in combination with the increment/decrement instruction of a general-purpose register or a register pair, the addresses of the data memory can be updated as shown in fig. 3-3. examples 1. to compare data 50h through 57h with data 110h through 117h data1 equ 57h data2 equ 117h set1 mbe sel mb1 mov d, #data1 shr4 mov hl, #data2 and 0ffh loop : mov a, @dl ske a, @hl ; a = (hl)? br no ; no decs l ; yes, l l 1 br loop 2. to clear data memory of 00h through ffh clr1 mbe mov xa, #00h mov hl, #04h loop : mov @hl, a ; (hl) a incs l ; l l+1 br loop incs h ; h h+1 br loop
chapter 3 features of architecture and memory map 32 user s manual u10201ej2v4um00 fig. 3-3 updating address of static ram 0 h f h @dl 4-bit transfer decs d incs d decs l incs l @hl 4-bit manipulation 8-bit manipuiation decs h incs h decs l incs l auto decrement auto increment decs hl incs hl direct addressing bit manipulation 4-bit transfer 8-bit transfer decs d incs d decs e incs e decs de incs de @h+mem. bit manipulation decs h incs h @de 4-bit transfer 0h fh
chapter 3 features of architecture and memory map 33 user s manual u10201ej2v4um00 (5) 8-bit register indirect addressing (@hl) this addressing mode is used to indirectly address the entire data memory space in 8-bit units by using a data pointer (hl register pair). in this addressing mode, data is processed in 8-bit units, that is, the 4-bit data at an address specified by the data pointer with bit 0 (bit 0 of the l register) cleared to 0 and the 4-bit data at the address higher are used in pairs and processed with the data of the 8-bit accumulator (xa register). the memory bank is specified in the same manner as when the hl register is specified in the 4-bit register indirect addressing mode, by using mbe and mbs. this addressing mode is applicable to the mov, xch, and ske instructions. examples 1. to compare whether the count register (t0) value of timer/event counter 0 is equal to the data at addresses 30h and 31h data equ 30h clr1 mbe mov hl, #data mov xa, t0 ; xa count register 0 ske a, @hl ; a = (hl)? br no incs l mov a, x ; a x ske a, @hl ; a = (hl)? 2. to clear data memory at 00h through ffh clr1 mbe mov xa, #00h mov hl, #04h loop : mov @hl, a ; (hl) a incs l br loop incs h br loop
chapter 3 features of architecture and memory map 34 user s manual u10201ej2v4um00 (i) set1 cy ; cy 1 and1 cy, port3.0 ; cy p30 and1 cy, port4.1 ; cy p41 skt cy ; cy = 1? br setp clr1 port5.3 ; p53 0 setp : set1 port5.3 ; p53 1 (ii) skt port3.0 ; p30 = 1? br setp skt port4.1 ; p41 = 1? br setp clr1 port5.3 ; p53 0 setp: set1 port5.3 ; p53 1 (6) bit manipulation addressing this addressing mode is used to manipulate the entire memory space in bit units (such as boolean processing and bit transfer). while the 1-bit direct addressing mode can be only used with the instructions that set, reset, or test a bit, this addressing mode can be used in various ways such as boolean processing by the and1, or1, and xor1 instructions, and test and reset by the sktclr instruction. bit manipulation addressing can be implemented in the following three ways, which can be selected depending on the data memory address to be used. (a) specific address bit direct addressing (fmem.bit) this addressing mode is to manipulate the hardware units that use bit manipulation especially often, such as i/o ports and interrupt-related flags, regardless of the setting of the memory bank. therefore, the data memory addresses to which this addressing mode is applicable are ff0h through fffh, to which the i/o ports are mapped, and fb0h through fbfh, to which the interrupt-related hardware units are mapped. the hardware units in these two data memory areas can be manipulated in bit units at any time in the direct addressing mode, regardless of the setting of mbs and mbe. examples 1. to test timer 0 interrupt request flag (irqt0) and, if it is set, clear the flag and reset p63 sktclr irqt0 ; irqt0 = 1? br no ; no clr1 port6.3 ; yes 2. to reset p53 if both p30 and p41 pins are 1 p30 p41 p53
chapter 3 features of architecture and memory map 35 user s manual u10201ej2v4um00 (b) specific address bit register indirect addressing (pmem, @l) this addressing mode is to indirectly specify and successively manipulate the bits of the peripheral hardware units such as i/o ports. the data memory addresses to which this addressing mode can be applied are fc0h through fffh. this addressing mode specifies the higher 10 bits of a 12-bit data memory address directly by using an operand, and the lower 2 bits by using the l register. therefore, 16 bits (4 ports) can be successively manipulated depending on the specification of the l register. this addressing mode can also be used independently of the setting of mbe and mbs. example to output pulses to the respective bits of ports 4 to 7 mov l, #0 loop : set1 port4.@l; bits of ports 4-7 (l 1-0 ) 1 clr1 port4.@l; bits of ports 4-7 (l 1-0 ) 0 incs l nop br loop p40 p41 p73 ~
chapter 3 features of architecture and memory map 36 user s manual u10201ej2v4um00 flag1 equ 30h.3 flag2 equ 31h.0 flag3 equ 32h.2 sel mb0 mov h, #flag1 shr 6 clr1 cy ; cy 0 or1 cy, @h+flag1 ; cy cy flag1 xor1 cy, @h+flag2 ; cy cy flag2 set1 @h+flag3 ; flag3 1 skt cy ; cy = 1? clr1 @h+flag3 ; flag3 0 (c) special 1-bit direct addressing (@h+mem.bit) this addressing mode enables bit manipulation in the entire memory space. the higher 4 bits of the data memory address of the memory bank specified by mbe and mbs are indirectly specified by the h register, and the lower 4 bits and the bit address are directly specified by the operand. this addressing mode can be used to manipulate the respective bits of the entire data memory area in various ways. example to reset bit 2 (flag3) at address 32h if both bits 3 (flag1) at address 30h and bit 0 (flag2) at address 31h are 0 or 1 flag1 flag2 flag3
chapter 3 features of architecture and memory map 37 user s manual u10201ej2v4um00 (7) stack addressing this addressing mode is used to save or restore data when interrupt service or subroutine processing is executed. the address of data memory bank 0 pointed to by the stack pointer (8 bits) is specified in this addressing mode. in addition to being used during interrupt service or subroutine processing, this addressing is also used to save or restore register contents by using the push or pop instruction. examples 1. to save or restore register contents during subroutine processing sub : push xa push hl push bs ; saves mbs pop bs pop hl pop xa ret 2. to transfer contents of register pair hl to register pair de push hl pop de ; de hl 3. to branch to address specified by registers [xabc] push bc push xa ret ; to branch address xabc
chapter 3 features of architecture and memory map 38 user s manual u10201ej2v4um00 3.2 bank configuration of general-purpose registers the pd753036 is provided with four register banks with each bank consisting of eight general-purpose registers: x, a, b, c, d, e, h, and l. the general-purpose register area consisting of these registers is mapped to the addresses 00h through 1fh of memory bank 0 (refer to fig. 3-5 configuration of general-purpose register (in 4-bit processing) ). to specify a general-purpose register bank, a register bank enable flag (rbe) and a register bank select register (rbs) are provided. rbs selects a register bank, and rbe determines whether the register bank selected by rbs is valid or not. the register bank (rb) that is enabled when an instruction is executed is as follows: rb = rbe rbs table 3-2 register bank selected by rbe and rbs rbs 3210 000 fixed to bank 0 1 0000 bank 0 selected 0 1 bank 1 selected 1 0 bank 2 selected 1 1 bank 3 selected rbe register bank fixed to 0 remark = don t care rbe is automatically saved or restored during subroutine processing and therefore can be set while subroutine processing is under execution. when interrupt service is executed, rbe is automatically saved or restored, and rbe can be set during interrupt service depending on the setting of the interrupt vector table as soon as the interrupt service is started. consequently, if different register banks are used for normal processing and interrupt service as shown in table 3-3, it is not necessary to save or restore general-purpose registers when an interrupt is serviced, and only rbs needs to be saved or restored if two interrupts are nested. this means that the interrupt service speed can be increased. table 3-3 example of using different register banks for normal routine and interrupt routine normal processing uses register banks 2 or 3 with rbe = 1 single interrupt service uses register bank 0 with rbe = 0 nesting service of two uses register bank 1 with rbe = 1 interrupts (at this time, rbs must be saved or restored) nesting service of three registers must be saved or restored by push or pop instructions or more interrupts .
chapter 3 features of architecture and memory map 39 user s manual u10201ej2v4um00 fig. 3-4 example of using register banks if rbs is to be changed in the course of subroutine processing or interrupt service, it must be saved or restored by using the push or pop instruction. rbe is set by using the set1 or clr1 instruction. rbs is set by using the sel instruction. example set1 rbe ; rbe 1 clr1 rbe ; rbe 0 sel rb0 ; rbs 0 sel rb3 ; rbs 3 the general-purpose register area provided to the pd753036 can be used not only as 4-bit registers but also as 8-bit register pairs. this feature allows the pd753036 to provide transfer, operation, comparison, and increment/ decrement instructions comparable to those of 8-bit microcontrollers and allows you to program using mainly only general-purpose registers.
chapter 3 features of architecture and memory map 40 user s manual u10201ej2v4um00 (1) to use as 4-bit registers when the general-purpose register area is used as a 4-bit register area, a total of eight general-purpose registers, x, a, b, c, d, e, h, and l, specified by rbe and rbs can be used as shown in fig. 3-5. of these registers, a plays a central role in transferring, operating, and comparing 4-bit data as a 4-bit accumulator. the other registers can transfer, compare, and increment or decrement data with the accumulator. (2) to use as 8-bit registers when the general-purpose register area is used as an 8-bit register area, a total of eight 8-bit register pairs can be used as shown in fig. 3-6: register pairs xa, bc, de, and hl of a register bank specified by rbe and rbs, and register pairs xa , bc , de , and hl of the register bank whose bit 0 is complemented in respect to the register bank (rb). of these register pairs, xa serves as an 8-bit accumulator, playing the central role in transferring, operating, and comparing 8-bit data. the other register pairs can transfer, compare, and increment or decrement data with the accumulator. the hl register pair is mainly used as a data pointer. the de and dl register pairs are also used as auxiliary data pointers. examples 1. incs hl ; skips if hl hl+1, hl=00h adds xa, bc ; skips if xa xa+bc and carry occurs subc de , xa ; de de xa cy mov xa, xa ; xa xa movt xa, @pcde ; xa (pc 13 8 +de) rom, table reference ske xa, bc ; skips if xa = bc 2. to test whether the value of the count register (t0) of timer/event counter is greater than the value of register pair bc and, if not, wait until it becomes greater clr1 mbe no : mov xa, t0 ; reads count register subs xa, bc ; xa bc? br yes ; yes br no ; no
chapter 3 features of architecture and memory map 41 user s manual u10201ej2v4um00 fig. 3-5 configuration of general-purpose registers (in 4-bit processing) x h d b x h d b x h d b x h d b 01h 03h 05h 07h 09h 0bh 0dh 0fh 11h 13h 15h 17h 19h 1bh 1dh 1fh a l e c a l e c a l e c a l e c 00h 02h 04h 06h 08h 0ah 0ch 0eh 10h 12h 14h 16h 18h 1ah 1ch 1eh register bank 1 (rbe . rbs = 1) register bank 0 (rbe . rbs = 0) register bank 2 (rbe . rbs = 2) register bank 3 (rbe . rbs = 3)
chapter 3 features of architecture and memory map 42 user s manual u10201ej2v4um00 fig. 3-6 configuration of general-purpose registers (in 8-bit processing) xa hl de bc xa hl de bc 00h 02h 04h 06h 08h 0ah 0ch 0eh when rbe . rbs = 0 xa hl de bc xa hl de bc 10h 12h 14h 16h 18h 1ah 1ch 1eh when rbe . rbs = 2 xa hl de bc xa hl de bc 00h 02h 04h 06h 08h 0ah 0ch 0eh when rbe . rbs = 1 xa hl de bc xa hl de bc 10h 12h 14h 16h 18h 1ah 1ch 1eh when rbe . rbs = 3
chapter 3 features of architecture and memory map 43 user s manual u10201ej2v4um00 3.3 memory-mapped i/o the pd753036 employs memory-mapped i/o that maps peripheral hardware units such as i/o ports and timers to addresses f80h through fffh on the data memory space, as shown in fig. 3-2. therefore, no special instructions to control the peripheral hardware units are provided, and all the hardware units are controlled by using memory manipulation instructions. (some mnemonics that make the program easy to read are provided for hardware control.) to manipulate peripheral hardware units, the addressing modes shown in table 3-4 can be used. the display data memory mapped to addresses 1ech through 1ffh is manipulated by specifying memory bank 1. table 3-4 addressing modes applicable to peripheral hardware unit manipulation applicable addressing mode hardware units bit manipulation specified in direct addressing mode mem.bit with all hardware units that can be mbe = 0 or (mbe = 1, mbs = 15) manipulated in 1-bit units specified in direct addressing mode fmem.bit regardless ist1, ist0, mbe, rbe of setting of mbe and mbs ie , irq , portn. specified in indirect addressing mode pmem.@l bsbn. regardless of setting of mbe and mbs portn. 4-bit manipulation specifies in direct addressing mode mem with mbe=0 all hardware units that can be or (mbe = 1 , mbs = 15) manipulated in 4-bit units specified in register indirect addressing @hl with (mbe = 1, mbs = 15) 8-bit manipulation specified in direct addressing mem with mbe = 0 or all hardware units that can be (mbe = 1, mbs = 15), where mem is even number. manipulated in 8-bit units specified in register indirect addressing @hl with mbe = 1, mbs = 15, where contents of l register are even number example clr1 mbe ; mbe = 0 set1 tm0. 3 ; starts timer 0 ei ie0 ; enables int0 di ie1 ; disables int1 sktclr irq2 ; tests and clears int2 request flag set1 port4, @l ; sets port 4 in a, port0 ; a port 0 out port4, xa ; port 5, 4 xa
chapter 3 features of architecture and memory map 44 user s manual u10201ej2v4um00 fig. 3-7 shows the i/o map of the pd753036. the meanings of the symbols shown in this figure are as follows: abbreviation .... name indicating the address of an internal hardware unit it can be written in operands of instructions r/w ................. indicates whether a hardware unit in question can be read or written r/w : read/write r : read only w : write only bits for manipulation .............. indicates the bit units in which a hardware unit in question can be manipulated : can be manipulated in specified units (1, 4, or 8 bits) : only some bits can be manipulated. for the bits that can be manipulated, refer to remark. : cannot be manipulated in specified units (1, 4, or 8 bits). bit manipulation addressing ... indicates a bit manipulation addressing mode that can be used to manipulate a hardware unit in question in 1-bit units
chapter 3 features of architecture and memory map 45 user s manual u10201ej2v4um00 address r/w remark register bank select register (rbs) bank select register (bs) memory bank select register (mbs) fig. 3-7 pd753036 i/o map (1/5) hardware name (abbreviation) bits for manipulation bit manipulation b3 b2 b1 b0 1 bit 4 bits 8 bits addressing f80h stack pointer (sp) r/w bit 0 is fixed to 0 f82h r note 1 f83h f84h stack bank select register (sbs) r/w only bit 3 can be manipulated f86h basic interval timer (bt) r f88h modulo register for setting high-level period of r/w timer/event counter (tmod2h) f8bh wdtm note2 w mem.bit only bit 3 can be (w) manipulated f8eh display control register (lcdc) r/w notes 1. rbs and mbs can be manipulated separately in 4-bit units. only bs can be manipulated in 8-bit units. write data to mbs and rbs by using the sel mbn and sel rbn instructions, respectively. 2. wdtm: watchdog timer enable flag (w): this flag cannot be set by an instruction when it has been once set. f85h basic interval timer mode register (btm) w mem.bit f8ch display mode register (lcdm) r/w mem.bit - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
chapter 3 features of architecture and memory map 46 user s manual u10201ej2v4um00 address r/w remark toe2 remc nrzb nrz timer/event counter 2 control register (tc2) tgce only bit 3 can be manipulated fig. 3-7 pd753036 i/o map (2/5) hardware name (abbreviation) bits for manipulation bit manipulation b3 b2 b1 b0 1 bit 4 bits 8 bits addressing only bit 3 can be (w) manipulated f91h f92h r/w mem.bit bit 3 is write-only f93h f94h timer/event counter 2 count register (t2) r f95h f96h timer/event counter 2 modulo register (tmod2) r/w f97h only bit 3 can be (r) manipulated f99h only bit 3 can be (w) manipulated fa2h toe0 note1 w mem.bit fa4h timer/event counter 0 count register (t0) r fa6h timer/event counter 0 modulo register (tmod0) r/w fa8h timer/event counter 1 mode register (tm1) r/w mem.bit only bit 3 can be (w) manipulated faah toe1 note2 w mem.bit fach timer/event counter 1 count register (t1) r faeh timer/event counter 1 modulo register (tmod1) r/w notes 1. toe0: timer/event counter 0 output enable flag (w) 2. toe1: timer/event counter 1 output enable flag (w) f90h timer/event counter 2 mode register (tm2) r/w mem.bit f98h watch mode register (wm) r/w mem.bit - - - - - - - - - fa0h timer/event counter 0 mode register (tm0) r/w mem.bit - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
chapter 3 features of architecture and memory map 47 user s manual u10201ej2v4um00 fig. 3-7 pd753036 i/o map (3/5) hardware name (abbreviation) bits for manipulation bit manipulation b3 b2 b1 b0 1 bit 4 bits 8 bits addressing fb0h r/w fmem.bit can only be read in 8-bit units (r) fb2h interrupt priority select register (ips) r/w note 1 (w) fb4h int0 edge detection mode register (im0) r/w only bit 0 can be manipulated only bits 0 and 1 can be manipulated only bits 0 and 3 can be manipulated inta register (inta) ie4 irq4 iebt irqbt intc register (intc) iew irqw inte register (inte) iet1 irqt1 iet0 irqt0 intf register (intf) iet2 irqt2 iecsi irqcsi intg register (intg) ie1 irq1 ie0 irq0 inth register (inth) ie2 irq2 fc0h bit sequential buffer 0 (bsb0) r/w mem.bit fc1h bit sequential buffer 1 (bsb1) r/w pmem.@l fc2h bit sequential buffer 2 (bsb2) r/w fc3h bit sequential buffer 3 (bsb3) r/w fcfh suboscillation circuit control register (sos) r/w remarks 1. ie indicates an interrupt enable flag. 2. ieq indicates an interrupt request flag. notes 1. only bit 3 can be manipulated by the ei and di instructions. 2. bits 3 and 2 can be manipulated when the stop or halt instruction is executed. address r/w remark ist1 ist0 mbe rbe program status word (psw) cy sk2 sk1 sk0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (r/w) (r/w) fbah r/w fbeh r/w - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fbch r/w - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fb8h r/w fmem.bit fbdh r/w fbfh r/w - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fb7h system clock control register (scc) r/w fb3h processor clock control register (pcc) r/w note 2 fb6h int2 edge detection mode register (im2) r/w fb5h int1 edge detection mode register (im1) r/w
chapter 3 features of architecture and memory map 48 user s manual u10201ej2v4um00 fig. 3-7 pd753036 i/o map (4/5) hardware name (abbreviation) bits for manipulation bit manipulation b3 b2 b1 b0 1 bit 4 bits 8 bits addressing fd0h clock output mode register (clom) w soc eoc a/d conversion mode register (adm) aden fdah sa register (sa) r fdch pull-up resistor specification register group a w (poga) fdeh pull-up resistor specification register group b w (pogb) fe0h serial operation mode register (csim) r/w note (r) (w) cmdd reld cmdt relt r/w mem.bit some bits can be sbi control register (sbic) read/written bsye ackd acke ackt fe4h serial i/o shift register (sio) r/w fe6h slave address register (sva) r/w pm33 pm32 pm31 pm30 w port mode register group a (pmga) pm63 pm62 pm61 pm60 pm2 w port mode register group b (pmgb) pm7 pm5 pm4 pm8 w port mode register group c (pmgc) note some bits can be read or written in 1-bit units. csie coi wup mem.bit fe2h address r/w remark fd8h r/w note r/w - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - feeh fech fe8h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
chapter 3 features of architecture and memory map 49 user s manual u10201ej2v4um00 fig. 3-7 pd753036 i/o map (5/5) hardware name (abbreviation) bits for manipulation bit manipulation b3 b2 b1 b0 1 bit 4 bits 8 bits addressing ff0h port 0 (port0) r fmem.bit ff1h port 1 (port1) r pmem.@l ff2h port 2 (port2) r/w ff3h port 3 (port3) r/w ff4h port 4 (port4) r/w ff5h port 5 (port5) r/w kr3 kr2 kr1 kr0 port 6 (port6) kr7 kr6 kr5 kr4 port 7 (port7) ff8h port 8 (port8) r/w address r/w remark ff6h r/w ff7h r/w - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
50 user s manual u10201ej2v4um00 [memo]
51 user? manual u10201ej2v4um00 chapter 4 internal cpu function 4.1 function to select mki and mkii modes 4.1.1 difference between mki and mkii modes the cpu of the pd753036 has two modes to be selected: mki and mkii modes. these modes can be selected by using the bit 3 of the stack bank select register (sbs). mki mode : in this mode, the pd753036 is upward-compatible with the pd75336. this mode can be used with the cpu in the 75xl series having a rom capacity of up to 16k bytes. mkii mode : in this mode, the pd753036 is not compatible with the pd75336. this mode can be used with all the cpus in the 75xl series, including the models having a rom capacity of 16k bytes or higher. table 4-1 differences between mki and mkii modes mki mode mkii mode program memory (bytes) 16384 number of stack bytes of 2 bytes 3 bytes subroutine instruction bra !addr1 instruction none provided calla !addr1 instruction movt xa, @bcxa instruction provided provided movt xa, @bcde instruction br bcxa instruction br bcde instruction call !addr instruction 3 machine cycles 4 machine cycles callf !faddr instruction 2 machine cycles 3 machine cycles caution mkii mode is for maintaining software compatibility with series such as the 75x and 75xl where the program memory exceeds 24k bytes. consequently, where rom efficiency and speed are important, please use mki mode.
chapter 4 internal cpu function 52 user? manual u10201ej2v4um00 4.1.2 setting stack bank select register (sbs) the mki mode or mkii mode is selected by using the stack bank select register (sbs). fig. 4-1 shows the format of this register. the stack bank select register is set by using a 4-bit memory manipulation instruction. to use the mki mode, be sure to initialize the stack bank select register to 10 b note at the beginning of the program. to use the mkii mode, initialize the register to 00 b note . fig. 4-1 format of stack bank select register note set the desired value at . caution the sbs.3 bit is set to ??after the reset signal has been asserted. therefore, the cpu operates in the mki mode. to use the instructions in the mkii mode, clear sbs.3 to ??to set the mkii mode. 32 address 10 0 memory bank 0 sbs sbs0 f84h sbs1 sbs3 sbs2 symbol specifies stack area 0 0 memory bank 1 1 1 memory bank 2 0 1 setting prohibited. 1 0 be sure to clear bit 2 to 0. 0 mkll mode selects mode 1 mkl mode
chapter 4 internal cpu function 53 user s manual u10201ej2v4um00 4.2 program counter (pc) ?14 bits this is a binary counter that holds an address of the program memory. fig. 4-2 configuration of program counter the value of the program counter (pc) is usually automatically incremented by the number of bytes of an instruction each time that instruction has been executed. when a branch instruction (br, bra, or brcb) is executed, immediate data indicating the branch destination address or the contents of a register pair are loaded to all or some bits of the pc. when a subroutine call instruction (call, calla, or callf) is executed or when a vectored interrupt occurs, the contents of the pc (a return address already incremented to fetch the next instruction) are saved to the stack memory (data memory specified by the stack pointer). then, the jump destination address is loaded to the pc. when the return instruction (ret, rets, or reti) instruction is executed, the contents of the stack memory are set to the pc. with the pd753036 and 75p3036, the contents of the lower 6 bits of address 0000h of the program memory are loaded to bits pc13 through pc8, and the contents of address 0001h are loaded to pc7 through pc0 when the reset signal is asserted. therefore, the program can be started from any address. pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0
chapter 4 internal cpu function 54 user s manual u10201ej2v4um00 4.3 program memory (rom) ?16384 8 bits the program memory stores a program, interrupt vector table, the reference table of the geti instruction, and table data. the program memory is addressed by the program counter. the table data can be referenced by using a table reference instruction (movt). fig. 4-3 shows address ranges in which execution can be branched by a branch or subroutine call instruction. a relative branch instruction (br $addr1 instruction) can branch execution to an address of [contents of pc 15 to 1 or +2 to +16], regardless of the block boundary. the address range of the program memory of each model is as follows: 0000h-3fffh : pd753036, 75p3036 special functions are assigned to the following addresses. all the addresses other than 0000h and 0001h can be usually used as program memory addresses. addresses 0000h and 0001h these addresses store a start address from which program execution is to be started when the reset signal is asserted, and a vector table to which the set values of rbe and mbe are written. program execution can be reset and started from any address. addresses 0002h through 000dh these addresses store start addresses from which program execution is to be started when a vector interrupt occurs, and a vector table to which the set values of rbe and mbe are written. interrupt service can be started from any address. addresses 0020h-007fh these addresses constitute a table area that can be referenced by the geti instruction note . note the geti instruction implements any 2- or 3-byte instruction, or two 1-byte instructions with 1 byte. it is used to decrease the number of program steps (refer to 10.1.1 geti instruction ).
chapter 4 internal cpu function 55 user s manual u10201ej2v4um00 fig. 4-3 program memory map note bra !addr1 and calla !addr1 instructions can be used in the mkii mode only. remark with instructions other than above, execution can be branched to an address specified by the pc with only the lower 8 bits changed, by using the br pcde or br pcxa instruction. 765 mbe mbe mbe mbe mbe mbe mbe rbe rbe rbe rbe rbe rbe rbe (higher 6 bits) (lower 8 bits) (higher 6 bits) (lower 8 bits) (higher 6 bits) (lower 8 bits) (higher 6 bits) (lower 8 bits) (higher 6 bits) (lower 8 bits) (higher 6 bits) (lower 8 bits) (higher 6 bits) (lower 8 bits) 0000h 0002h 0004h 0006h 0008h 000ah 000ch reference table of geti instruction branch address of the following instructions: call ! addr instruction subroutine entry address br $addr instruction relative branch address ( _ 15 to _ 1, +2 to +16) brcb ! caddr instruction branch address brcb ! caddr instruction branch address brcb !caddr instruction branch address callf ! faddr instruction entry address branch destination address of geti instruction, subroutine entry address 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 3fffh 0 internal reset start address internal reset start address intbt/lnt4 start address intbt/lnt4 start address int0 start address int0 start address int1 start address int1 start address intcsi start address intcsi start address intt0 start address intt0 start address intt1, intt2 start address intt1, intt2 start address 2fffh 3000h brcb ! caddr instruction branch address . br bcxa . br bcde . br ! addr . bra ! addr 1 note . calla ! addr 1 note
chapter 4 internal cpu function 56 user s manual u10201ej2v4um00 4.4 data memory (ram) ... 768 words 4 bits the data memory consists of data areas and a peripheral hardware area as shown in fig. 4-4. the data memory consists the following banks with each bank made up of 256 words 4 bits: memory banks 0, 1 and 2 (data areas) memory bank 15 (peripheral hardware area) 4.4.1 configuration of data memory (1) data area a data area consists of a static ram and is used to store data, and as a stack memory when a subroutine or interrupt is executed. the contents of this area can be retained for a long time by battery backup even when the cpu is halted in standby mode. the data area is manipulated by using memory manipulation instructions. static ram is mapped to memory banks 0, 1 and 2 in units of 256 4 bits each. although bank 0 is mapped as a data area, it can also be used as a general-purpose register area (000h through 01fh) and as a stack area note 1 (000h through 2ffh). bank 1 can be used as a display data memory (1ech through 1ffh). one address of the static ram consists of 4 bits. however, it can be manipulated in 8-bit units by using an 8-bit memory manipulation instruction or in 1-bit units by using a bit manipulation instruction note 2 ). to use an 8-bit manipulation instruction, specify an even address. notes 1. one stack area can be selected from memory bank 0-2. 2. the display data memory cannot be manipulated in 8-bit units. general-purpose register area this area can be manipulated by using a general-purpose register manipulation instruction or memory manipulation instruction. up to eight 4-bit registers can be used. the registers not used by the program can be used as part of the data area or stack area. stack area the stack area is set by an instruction and is used as a saving area when a subroutine or interrupt service is executed. display data memory the display data of an lcd are written to this area. the data written to this display data memory are automatically read and displayed by hardware when the lcd is driven. the addresses of this area not used for display can be used as data area addresses. (2) peripheral hardware area the peripheral hardware area is mapped to addresses f80h through fffh of memory bank 15. this area is manipulated by using a memory manipulation instruction, in the same manner as the static ram. note, however, that the bit units in which the peripheral hardware units can be manipulated differ depending on the address. the addresses to which no peripheral hardware unit is allocated cannot be accessed because these addresses are not provided to the data memory.
chapter 4 internal cpu function 57 user s manual u10201ej2v4um00 4.4.2 specifying bank of data memory a memory bank is specified by a 4-bit memory bank select register (mbs) when bank specification is enabled by setting a memory bank enable flag (mbe) to 1 (mbs = 0, 1, 2, or 15). when bank specification is disabled (mbe = 0), bank 0 or 15 is automatically specified depending on the addressing mode selected at that time. the addresses in the bank are specified by 8-bit immediate data or a register pair. for the details of memory bank selection and addressing, refer to 3.1 bank configuration of data memory and addressing mode . for how to use a specific area of the data memory, refer to the following: general-purpose register area .... 4.5 general-purpose register stack area .................................... 4.7 stack pointer (sp) and stack bank select register (sbs) display data memory ................... 5.7.5 display data memory peripheral hardware area ........... chapter 5 peripheral hardware function
chapter 4 internal cpu function 58 user s manual u10201ej2v4um00 fig. 4-4 data memory map note one of memory banks 0 through 2 can be selected as the stack area. (32 4) 0 01fh 020h 000h 0ffh 100h 1ebh 1ech 1ffh 200h 2ffh 1 2 256 4 (224 4) 256 4 (236 4) (20 4) 256 4 data area static ram (768 4) stack area note general-purpose register area display data memory data memory memory bank 15 f80h fffh 128 4 peripheral hardware area not provided
chapter 4 internal cpu function 59 user s manual u10201ej2v4um00 the contents of the data memory are undefined at reset. therefore, they must be initialized at the beginning of program execution (ram clear). otherwise, unexpected bugs may occur. example to clear ram at addresses 000h through 1ffh set1 mbe sel mb0 mov xa, #00h mov hl, #04h ramc0 : mov @hl, a ; clears 04h-ffh note incs l ; l l+1 br ramc0 incs h ; h h+1 br ramc0 sel mb1 ramc1 : mov @hl, a ; clears 100h-1ffh incs l ; l l+1 br ramc1 incs h ; h h+1 br ramc1 note data memory addresses 000h through 003h are not cleared because they are used as general-purpose register pairs xa and hl.
chapter 4 internal cpu function 60 user s manual u10201ej2v4um00 fig. 4-5 configuration of display data memory the display data memory is manipulated in 1- or 4-bit units. caution the display data memory cannot be manipulated in 8-bit units. example to clear display data memory at addresses 1e0h-1ffh set1 mbe sel mb1 mov hl, #0e0h mov a, #00h loop : mov @hl, a ; clears display data memory in 4-bit units all at once incs l br loop incs h br loop 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 s24/bp0 s25/bp1 s26/bp2 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 com0 com1 com2 com3 1ech 1edh 1eeh 1efh s12 s13 s14 s15 b 0 b 1 b 2 b 3 address display data memory segment output/bit port output common signal
chapter 4 internal cpu function 61 user s manual u10201ej2v4um00 4.5 general-purpose register ... 8 4 bits 4 banks general-purpose registers are mapped to the specific addresses of the data memory. four banks of registers, with each bank consisting of eight 4-bit registers (b, c, d, e, h, l, x, and a), are available. the register bank (rb) that becomes valid when an instruction is executed is determined by the following expression: rb = rbe rbs (rbs = 0-3) each general-purpose register is manipulated in 4-bit units. moreover, two registers can be used in pairs, such as bc, de, hl, and xa, and manipulated in 8-bit units. register pairs de, hl, and dl are also used as data pointers. when registers are manipulated in 8-bit units, the register pairs of the register bank (rb) with bit 0 inverted (0 ? 1, 2 ? 3), bc , de , hl , and xa , can also be used in addition to bc, de, hl, and xa (refer to 3.2 bank configuration of general-purpose registers ). the general-purpose register are can be addressed and accessed as an ordinary ram area, regardless of whether the registers in this area are used or not. fig. 4-6 configuration of general-purpose register fig. 4-7 configuration of register pair . 000h 001h 002h 003h 004h 005h 006h 007h 008h 00fh 010h 017h 018h . . . . . 01fh same configura- tion as bank 0 same configura- tion as bank 0 same configura- tion as bank 0 register bank 0 register bank 1 register bank 2 register bank 3 0 3 address data memory a register x register l register h register e register d register c register b register . . . . . . . . . 0 3 b 0 3 c 0 3 d 0 3 e 0 3 h 0 3 l 0 3 x 0 3 a one bank
chapter 4 internal cpu function 62 user s manual u10201ej2v4um00 4.6 accumulator with the pd753036, the a register or xa register pair functions as an accumulator. the a register plays a central role in 4-bit data processing, while the xa register pair is used for 8-bit data processing. when a bit manipulation instruction is used, the carry flag (cy) is used as a bit accumulator. fig. 4-8 accumulator 4.7 stack pointer (sp) and stack bank select register (sbs) the pd753036 uses a static ram as the stack memory (lifo). the stack pointer (sp) is an 8-bit register that holds information on the first address of the stack area. the stack area consists of addresses 000h through 2ffh of memory bank 0, 1, or 2. one memory bank is specified by 2-bit sbs (refer to table 4-2 ). table 4-2 stack area selected by sbs sbs sbs1 sbs2 0 0 memory bank 0 0 1 memory bank 1 1 0 memory bank 2 1 1 setting prohibited the value of sp is decremented before data is written (saved) to the stack area, and is incremented after data has been read (restored) from the stack memory. the data saved or restored to or from the stack are as shown in figs. 4-10 through 4-13. the initial values of sp and sbs are respectively set by an 8-bit memory manipulation instruction and 4-bit memory manipulation instruction, to determined the stack area. the values of sp and sbs can also be read. stack area - - - - - - - - - - - - - - - cy bit accumulator a 4-bit accumulator a 8-bit accumulator x
chapter 4 internal cpu function 63 user s manual u10201ej2v4um00 when 00h is set to sp as the initial value, the memory bank (n) specified by sbs is used as the stack area, starting from the highest address (nffh). the stack area can be used only in the memory bank specified by sbs. if an attempt is made to use an area exceeding address n00h as the stack area, the address is returned to nffh in the same bank. this means that an area exceeding the boundary of a memory bank cannot be used as a stack area unless the value of sbs is rewritten. the contents of sp and sbs become undefined when the reset signal is asserted. therefore, be sure to initialize these to the desired values at the beginning of the program. fig. 4-9 configuration of stack pointer and stack bank select register note sbs3 can select mki or mkii mode. the stack bank select function can be used in both the mki and mkii modes (for details, refer to 4.1 function to select mki and mkii modes ). example to initialize sp to allocate stack area to memory bank 2 and use area starting from address 2ffh as stack sel mb15 ; or clr1 mbe mov a, #2 mov sbs, a ; specifies memory bank 2 as stack area mov xa, #00h mov sp, xa ; sp 00h 0 f80h sp1 sp3 sp2 sp4 sp5 sp6 sp7 address sp symbol sbs0 f84h sbs1 sbs3 note 0 sbs memory bank 0 000h 0ffh 100h 1ffh 200h 2ffh memory bank 1 memory bank 3 sbs sp sp sp
chapter 4 internal cpu function 64 user s manual u10201ej2v4um00 fig. 4-10 data saved to stack memory (mki mode) fig. 4-11 data restored from stack memory (mki mode) stack sp + 1 sp + 2 pop instruction stack pc11-pc8 pc3-pc0 pc7-pc4 ret, rets instruction stack reti instruction sp + 2 sp + 3 sp + 4 sp + 1 pc11-pc8 pc3-pc0 pc7-pc4 sp + 4 sp + 5 sp + 6 sp + 3 sp + 2 sp + 1 mbe rbe pc13 pc12 mbe rbe pc13 pc12 cy sk2 mbe rbe sk1 sk0 ist0 ist1 psw sp register pair, low register pair, high sp sp stack sp _ 1 sp push instruction stack pc11-pc8 pc3-pc0 pc7-pc4 call, callf instruction stack interrupt sp _ 2 sp _ 1 sp sp _ 3 pc11-pc8 pc3-pc0 pc7-pc4 sp _ 2 sp _ 1 sp sp _ 3 sp _ 4 sp _ 5 mbe rbe pc13 pc12 mbe rbe pc13 pc12 cy sk2 mbe rbe sk1 sk0 ist0 ist1 psw sp _ 2 register pair, low register pair, high sp _ 4 sp _ 6
chapter 4 internal cpu function 65 user s manual u10201ej2v4um00 fig. 4-12 data saved to stack memory (mkii mode) fig. 4-13 data restored from stack memory (mkii mode) note the contents of psw other than mbe and rbe are not saved or restored. remark *: undefined stack sp _ 1 sp push instruction stack pc11-pc8 pc3-pc0 pc7-pc4 call, calla, callf instruction stack interrupt sp _ 4 sp _ 3 sp _ 2 sp _ 5 pc11-pc8 pc3-pc0 pc7-pc4 sp _ 2 sp _ 1 sp sp _ 3 sp _ 4 sp _ 5 00 pc13 pc12 00 pc13 pc12 cy sk2 mbe rbe sk1 sk0 ist0 ist1 psw sp _ 2 register pair, low register pair, high sp _ 6 sp _ 6 ** mbe rbe ** * * note sp _ 1 sp stack sp + 1 sp + 2 pop instruction stack pc11-pc8 pc3-pc0 pc7-pc4 ret, rets instruction stack reti instruction sp + 2 sp + 3 sp + 4 sp + 1 pc11-pc8 pc3-pc0 pc7-pc4 sp + 4 sp + 5 sp + 6 sp + 3 sp + 2 sp + 1 00 pc13 pc12 00 pc13 pc12 cy sk2 mbe rbe sk1 sk0 ist0 ist1 psw sp register pair, low register pair, high sp sp ** mbe rbe ** * * note sp + 5 sp + 6
chapter 4 internal cpu function 66 user s manual u10201ej2v4um00 4.8 program status word (psw) ... 8 bits the program status word (psw) consists of flags closely related to the operations of the processor. psw is mapped to addresses fb0h and fb1h of the data memory space, and the 4 bits of address fb0h can be manipulated by using a memory manipulation instruction. fig. 4-14 configuration of program status word table 4-3 psw flags saved/restored to/from stack flag saved or restored save when call, calla, or callf instruction is executed mbe and rbe are saved when hardware interrupt occurs all psw bits are saved restore when ret or rets instruction is executed mbe and rbe are restored when reti instruction is executed all psw bits are restored (1) carry flag (cy) the carry flag records the occurrence of an overflow or underflow when an operation instruction with carry (addc or subc) is executed. the carry flag also functions as a bit accumulator and can store the result of a boolean operation performed between a specified bit address and data memory. the carry flag is manipulated by using a dedicated instruction and is independent of the other psw bits. the carry flag becomes undefined when the reset signal is asserted. rbe mbe ist0 ist1 sk0 sk1 sk2 cy cannot be manipulated can be manipulated fb0h fb1h can be manipulated by dedicated instruction symbol psw address fb0h
chapter 4 internal cpu function 67 user s manual u10201ej2v4um00 table 4-4 carry flag manipulation instruction instruction (mnemonic) operation and processing of carry flag carry flag manipulation set1 cy sets cy to 1 instruction clr1 cy clears cy to 0 not1 cy inverts content of cy skt cy skips if content of cy is 1 bit transfer instruction mov1 mem*.bit, cy transfers content of cy to specified bit mov1 cy, mem*.bit transfers content of specified bit to cy bit boolean instruction and1 cy, mem*.bit takes ands, ors, or xors content of specified bit or1 cy, mem*.bit with content of cy and sets result to cy xor1 cy, mem*.bit interrupt service interrupt execution example saved to stack memory in parallel with other psw bits in 8-bit units reti restored from stack memory with other psw bits remark mem*.bit indicates the following three bit manipulation addressing modes: fmem.bit pmem.@l @h+mem.bit example to and bit 3 at address 3fh with p33 and output result to p50 mov h, #3h ; sets higher 4 bits of address to h register mov1 cy, @h+0fh.3 ; cy bit 3 of 3fh and1 cy, port3.3 ; cy cy p33 mov1 port5.0, cy ; p50 cy (2) skip flags (sk2, sk1, and sk0) the skip flags record the skip status, and are automatically set or reset when the cpu executes an instruction. these flags cannot be manipulated directly by the user as operands. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
chapter 4 internal cpu function 68 user s manual u10201ej2v4um00 (3) interrupt status flags (ist1 and ist0) the interrupt status flags record the status of the processing under execution (for details, refer to table 6-3 ist, ist0, and interrupt service ). table 4-5 contents of interrupt status flags ist1 ist0 status of processing being executed processing and interrupt control 0 0 status 0 normal program is being executed. all interrupts can be acknowledged 0 1 status 1 interrupt with lower or higher priority is serviced. only an interrupt with higher priority can be acknowledged 1 0 status 2 interrupt with higher priority is serviced. all interrupts are disabled from being acknowledged 11 setting prohibited the interrupt priority control circuit (refer to fig. 6-1 block diagram of interrupt control circuit ) identifies the contents of these flags and controls the nesting of interrupts. the contents of ist1 and 0 are saved to the stack along with the other bits of psw when an interrupt is acknowledged, and the status is automatically updated by one. when the reti instruction is executed, the values before the interrupt was acknowledged are restored to the interrupt status flags. these flags can be manipulated by using a memory manipulation instruction, and the processing status under execution can be changed by program. caution to manipulate these flags, be sure to execute the di instruction to disable the interrupts before manipulation. after manipulation, execute the ei instruction to enable the interrupts. (4) memory bank enable flag (mbe) this flag specifies the address information generation mode of the higher 4 bits of the 12 bits of a data memory address. mbe can be set or reset at any time by using a bit manipulation instruction, regardless of the setting of the memory bank. when this flag is set to 1 , the data memory address space is expanded, and the entire data memory space can be addressed. when mbe is reset to 0 , the data memory address space is fixed, regardless of mbs (refer to fig. 3-2 configuration of data memory and addressing ranges of respective addressing modes ). when the reset signal is asserted, the content of bit 7 of program memory address 0 is set. also, mbe is automatically initialized. when a vectored interrupt is serviced, the bit 7 of the corresponding vector address table is set. also, the status of mbe when the interrupt is serviced is automatically set. usually, mbe is reset to 0 for interrupt service, and the static ram in memory bank 0 is used.
chapter 4 internal cpu function 69 user s manual u10201ej2v4um00 (5) register bank enable flag (rbe) this flag specifies whether the register bank of the general-purpose registers is expanded or not. rbe can be set or reset at any time by using a bit manipulation instruction, regardless of the setting of the memory bank. when this flag is set to 1 , one of four general-purpose register banks 0 to 3 can be selected depending on the contents of the register bank select register (rbs). when rbe is reset to 0 , register bank 0 is always selected, regardless of the contents of the register bank select register (rbs). when the reset signal is asserted, the content of bit 6 of program memory address 0 is set to rbe, and rbe is automatically initialized. when a vectored interrupt occurs, the content of bit 6 of the corresponding vector address table is set to rbe. also, the status of rbe when the interrupt is serviced is automatically set. usually, rbe is reset to 0 during interrupt service. register bank 0 is selected for 4-bit processing, and register banks 0 and 1 are selected for 8-bit processing.
chapter 4 internal cpu function 70 user s manual u10201ej2v4um00 4.9 bank select register (bs) the bank select register (bs) consists of a register bank select register (rbs) and a memory bank select register (mbs) which specify the register bank and the memory bank to be used, respectively. rbs and mbs are set by the sel rbn and sel mbn instructions, respectively. bs can be saved to or restored from the stack area in 8-bit units by the push bs or pop bs instruction. fig. 4-15 configuration of bank select register (1) memory bank select register (mbs) the memory bank select register is a 4-bit register that records the higher 4 bits of a 12-bit data memory address. this register specifies the memory bank to be accessed. with the pd753036, however, only banks 0 through 2 and 15 can be specified. mbs is set by the sel mbn instruction (n = 0-2, 15). the address range specified by mbe and mbs is as shown in fig. 3-2. when the reset signal is asserted, mbs is initialized to 0 . (2) register bank select register (rbs) the register bank select register specifies a register bank to be used as general-purpose registers. it can select bank 0 to 3. rbs is set by the sel rbn instruction (n = 0-3). when the reset signal is asserted, rbs is initialized to 0 . table 4-6 rbe, rbs, and register bank selected rbs 3210 000 fixed to bank 0 1 0000 selects bank 0 0 1 selects bank 1 1 0 selects bank 2 1 1 selects bank 3 = don t care rbe register bank fixed to 0 rbs0 rbs1 0 0 mbs0 mbs1 mbs2 mbs3 f82h f83h symbol bs address f82h
71 user? manual u10201ej2v4um00 chapter 5 peripheral hardware function 5.1 digital i/o port the pd753036 uses memory mapped i/o, and all the i/o ports are mapped to the data memory space. fig. 5-1 data memory address of digital port table 5-2 lists the instructions that manipulate the i/o ports. ports 4 through 7 can be manipulated in 4-i/o, 8- i/o, and 1-bits. they are used for various control operations. bp0 through bp7 are 1-bit output ports. examples 1. to test the status of p13 and outputs different values to ports 4 and 5 depending on the result skt port1.3 ; skips if bit 3 of port 1 is 1 mov xa, #18h ; xa 18h mov xa, #14h ; xa 14h sel mb15 ; or clr1 mbe out port4, xa ; ports 5, 4 xa 2. set1 port4.@l ; sets the bits of ports 4 through 7 specified by the l register to ? string effect ff0h ff1h ff2h ff3h ff4h ff5h ff6h ff7h ff8h p03 p13 p23 p33 p43 p53 p63 p73 p83 address 3 p02 p12 p22 p32 p42 p52 p62 p72 p82 2 p01 p11 p21 p31 p41 p51 p61 p71 p81 1 p00 p10 p20 p30 p40 p50 p60 p70 p80 0 port0 port1 port2 port3 port4 port5 port6 port7 port8 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 bit port0 bit port1 bit port2 bit port3 bit port4 bit port5 bit port6 bit port7
chapter 5 peripheral hardware function 72 user s manual u10201ej2v4um00 port5 note1 (p50-p53) 5.1.1 types, features, and configurations of digital i/o ports table 5-1 shows the types of digital i/o ports. figs. 5-2 through 5-6 show the configuration of each port. table 5-1 types and features of digital ports port (pin name) port0 4-bit input can always be read or tested regardless of operation shared with int4, sck, (p00-p03) mode of shared pins so/sb0, and si/sb1 port1 shared with int0-int2, (p10-p13) and ti0 port2 4-bit i/o can be set in input or output mode in 4-bit units shared with pto0-pto2, (p20-p23) pcl, and buz port3 note1 can be set in input or output mode in 1- or 4-bit units shared with lcdcl, (p30-p33) sync, and md0-md3 note2 port4 note1 4-bit i/o can be set in input or ports 4 and 5 can be used pull-up resistor can be (p40-p43) (n-ch, open- output mode in 4-bit units in pairs to input/output connected in 1-bit units drain, 13 v) data in 8-bit units by mask option port6 4-bit i/o can be set in input or ports 6 and 7 can be used shared with kr0-kr3 (p60-p63) output mode in 1- or 4-bit in pairs to input or output units data in 8-bit units port7 can be set in input or shared with kr4-kr7 (p70-p73) output mode in 4-bit units port8 can be set in input or output mode in 4-bit units shared with ti1, ti2, an6 (p80-p83) and an7 bp0-bp7 1-bit output output data in 1-bit units. segment outputs for driving lcd s24-s31 can be selected by software notes 1. these ports can directly drive an led. 2. port 3 of the pd75p3036 is shared with the md0 through md3 pins. p10 is shared with an external vectored interrupt input pin and is provided with a noise rejection circuit (for details, refer to 6.3 hardware controlling interrupt function ). bp0 through bp7 are shared with segment output pins for driving lcd (s24 through s31). the functions of these pins are selected by the bits 6 and 7 of the display mode register (lcdm) in 4- or 8-bit units. bp0 through bp7 are bit output ports and output the data of the bits 0 of addresses 1f8h through 1ffh of the display data memory. (refer to 5.7.5 ) when the reset signal is asserted, the output latches of ports 2 through 8 are cleared, the output buffers are turned off, and the ports are set in the input mode. function operation and feature remark
chapter 5 peripheral hardware function 73 user s manual u10201ej2v4um00 fig. 5-2 configuration of ports 0 and 1 p13/ti0 p12/int2 p11/int1 p10/int0 input buffer with hysteresis characteristics noise rejection circuit int0 int1 int2 ti0 input buffer p03/si/sb1 p02/so/sb0 p01/sck p00/int4 int4 sck si selector csi internal bus 8 selector input buffer po1 output latch so sck bit 0 of poga p-ch v dd pull-up resistor output buffer that can select push-pull output and n-ch open- drain output bit 1 of poga p-ch pull-up resistor v dd or f x /64 selector internal n-ch open-drain output
chapter 5 peripheral hardware function 74 user s manual u10201ej2v4um00 fig. 5-3 configuration of ports 3 and 6 fig. 5-4 configuration of ports 2 and 7 corresponding bit of port mode register group a internal bus output latch pmmn output buffer mpx pmmn = 1 pmmn = 0 input buffer m = 3, 6 n = 0 _ 3 pmn bit m of poga v dd p-ch pull-up resistor input buffer with hysteresis characteristics (port 6 only) key interrupt (port 6 only) internal bus pm0 pm1 pm2 pm3 output latch corresponding bit of port mode register group b (m = 2, 7) output buffer pmm = 1 pmm = 0 mpx input buffer pmm bit m of poga pull-up resistor v dd input buffer with hysteresis characteristics (port 7 only) key interrupt (port 7 only) p-ch
chapter 5 peripheral hardware function 75 user s manual u10201ej2v4um00 fig. 5-5 configuration of ports 4 and 5 internal bus pm0 pm1 pm2 pm3 output latch corresponding bit of port mode register group b (m = 4, 5) open-drain output buffer pmm = 1 pmm = 0 mpx input buffer pmm v dd (mask option) pull-up resistor
chapter 5 peripheral hardware function 76 user s manual u10201ej2v4um00 fig. 5-6 configuration of port 8 internal bus p80/ti1 p81/ti2 p82/an6 p83/an7 output latch bit 0 of port mode register group c output buffer pm8 = 1 pm8 = 0 mpx input buffer pm8 bit 0 of pogb pull-up resistor v dd p-ch a/d converter
chapter 5 peripheral hardware function 77 user s manual u10201ej2v4um00 5.1.2 setting i/o mode the input or output mode of each i/o port is set by the corresponding port mode register as shown in fig. 5-7. ports 3 and 6 can be set in the input or output mode in 1-bit units by using port mode register group a (pmga). ports 2, 4, 5, and 7 are set by using port mode register group b (pmgb), and port 8 is set by using port mode register group c (pmgc) in the input or output mode in 4-bit units. each port is set in the input mode when the corresponding port mode register bit is 0 and in the output mode when the corresponding register bit is 1 . when a port is set in the output mode by the corresponding port mode register, the contents of the output latch are output to the output pin(s). before setting the output mode, therefore, the necessary value must be written to the output latch. port mode register groups a, b, and c are set by using an 8-bit memory manipulation instruction. when the reset signal is asserted, all the bits of each port mode register are cleared to 0, the output buffer is turned off, and the corresponding port is set in the input mode. example to use p30, 31, 62, and 63 as input pins and p32, 33, 60, and 61 as output pins clr1 mbe ; or sel mb15 mov xa, #3ch mov pmga, xa
chapter 5 peripheral hardware function 78 user s manual u10201ej2v4um00 fig. 5-7 format of each port mode register specification 0 input mode (output buffer off) 1 output mode (output buffer on) port mode register group a port mode register group b port mode register group c 765432 10 pm30 pm31 pm33 pm32 pm60 pm61 pm62 pm63 address pmga fe8h symbol sets p30 in input or output mode sets p31 in input or output mode sets p32 in input or output mode sets p33 in input or output mode sets p60 in input or output mode sets p61 in input or output mode sets p62 in input or output mode sets p63 in input or output mode 765432 10 _ _ _ pm2 pm4 pm5 _ pm7 address pmgb fech symbol sets port 2 (p20-p23) in input or output mode sets port 4 (p40-p43) in input or output mode sets port 5 (p50-p53) in input or output mode sets port 7 (p70-p73) in input or output mode 765432 10 pm8 _ __ _ _ _ _ address pmgc feeh symbol sets port 8 (p80-p83) in input or output mode
chapter 5 peripheral hardware function 79 user s manual u10201ej2v4um00 5.1.3 digital i/o port manipulation instruction because all the i/o ports of the pd753036 are mapped to the data memory space, they can be manipulated by using data memory manipulation instructions. table 5-2 shows these data memory manipulation instructions which are considered to be especially useful for manipulating the i/o pins and their range of applications. (1) bit manipulation instruction because the specific address bit direct addressing (fmem.bit) and specific address bit register indirect addressing (pmem.@l) are applicable to digital i/o ports 0 through 8, the bits of these ports can be manipulated regardless of the specifications by mbe and mbs. example to or p50 and p41 and set p61 in output mode mov1 cy, port5.0 ; cy p50 or1 cy, port4.1 ; cy cy p41 mov1 port6.1, cy ; p61 cy (2) 4-bit manipulation instruction in addition to the in and out instructions, all the 4-bit memory manipulation instructions such as mov, xch, adds, and incs can be used to manipulate the ports in 4-bit units. before executing these instructions, however, memory bank 15 must be selected. examples 1. to output the contents of the accumulator to port 3 sel mb15 ; or clr1 mbe out port3, a 2. to add the value of the accumulator to the data output to port 5 set1 mbe sel mb15 mov hl, #port5 adds a, @hl ; a a+port5 nop mov @hl, a ; port5 a 3. to test whether the data of port 4 is greater than the value of the accumulator set1 mbe sel mb15 mov hl, #port4 subs a, @hl ; a
chapter 5 peripheral hardware function 81 user s manual u10201ej2v4um00 table 5-2 list of i/o pin manipulation instructions port port port port port port port port port bit port 012345678 0-7 in a,portn note 1 mov a, mem note 3, 4 in xa,portn note 1 out portn, a note 1 mov mem, a note 3, 4 out portn, xa note 1 set1 portn.bit set1 bpn note 3 set1 portn.@l note 1 clr1 portn.bit clr1 bpn note 3 clr1 portn.@l note 1 skt portn.bit skt bpn note 3 skt portn.@l note 1 skf portn.bit skf bpn note 3 skf portn.@l note 1 mov1 cy, portn.bit mov1 cy, portn.@l note 2 mov1 portn.bit, cy mov1 portn.@l, cy note 2 and1 cy, portn.bit and1 cy, @h+bpn note 3, 5 and1 cy, portn.@l note 2 or1 cy, portn.bit or1 cy, @h+bpn note 3, 5 or1 cy, portn.@l note 2 xor1 cy, portn.bit xor1 cy, @h+bpn note 3, 5 xor1 cy, portn.@l note 2 notes 1. mbe = 0 or (mbe = 1, mbs = 15) before these instructions are executed. 2. the lower 2 bits of the address and the bit address are indirectly specified by the l register. 3. (mbe = 1, mbs = 1) before executing these instructions. 4. bit 0 of accumulator a corresponds to bpn. 5. write fh to the h register.
chapter 5 peripheral hardware function 82 user s manual u10201ej2v4um00 5.1.4 operation of digital i/o port the operations of each port and port pin when a data memory manipulation instruction is executed to manipulate a digital i/o port differ depending on whether the port is set in the input or output mode (refer to table 5-3 ). this is because, as can be seen from the configuration of the i/o port, the data of each pin is loaded to the internal bus in the input mode, and the data of the output latch is loaded to the internal bus in the output mode. (1) operation in input mode when a test instruction such as skt, a bit input instruction such as mov1, or an instruction that loads port data to the internal bus in 4- or 8-bit units, such as in, out, operation, or comparison instruction, is executed, the data of each pin is manipulated. when an instruction that transfers the contents of the accumulator in 4- or 8-bit units, such as out or mov, is executed, the data of the accumulator is latched to the output latch. the output buffer remains off. when the xch instruction is executed, the data of each pin is input to the accumulator, and the data of the accumulator is latched to the output latch. the output buffer remains off. when the incs instruction is executed, the data (4 bits) of each pin incremented by one (+1) is latched to the output latch. the output buffer remains off. when an instruction that rewrites the data memory contents in 1-bit units, such as set1, clr1, mov1, or sktclr, is executed, the contents of the output latch of the specified bit can be rewritten as specified by the instruction, but the contents of the output latches of the other bits are undefined. (2) operation in output mode when a test instruction, bit input instruction, or an instruction in 4- or 8-bit units that loads port data to the internal bus is executed, the contents of the output latch are manipulated. when an instruction that transfers the contents of the accumulator in 4- or 8-bit units is executed, the data of the output latch is rewritten and at the same time output from the port pins. when the xch instruction is executed, the contents of the output latch are transferred to the accumulator. the contents of the accumulator are latched to the output latches of the specified port and output from the port pins. when the incs instruction is executed, the contents of the output latches of the specified port are incremented by 1 and output from the port pins. when a bit output instruction is executed, the specified bit of the output latch is rewritten and output from the pin.
chapter 5 peripheral hardware function 83 user s manual u10201ej2v4um00 table 5-3 operation when i/o port is manipulated operation of port and pin input mode output mode skt <1> tests pin data test output latch data skf <1> mov1 cy, <1> transfers pin data to cy transfers output latch data to cy and1 cy, <1> performs operation between pin data and cy performs operation between output latch data or1 cy, <1> and cy xor1 cy, <1> in a, portn transfers pin data to accumulator transfers output latch data to accumulator in xa, portn mov a, @hl mov xa, @hl adds a, @hl performs operation between pin data and performs operation between output latch data addc a, @hl accumulator and accumulator subs a, @hl subc a, @hl and a, @hl or a, @hl xor a, @hl ske a, @hl compares pin data with accumulator compares output latch data with accumulator ske xa, @hl out portn, a transfers accumulator data to output latch transfers accumulator data to output latch and out portn, xa (output buffer remains off) outputs data from pins mov @hl, a mov @hl, xa xch a, portn transfers pin data to accumulator and accumulator exchanges data between output latch and xch xa, portn data to output latch (output buffer remains off) accumulator xch a, @hl xch xa, @hl incs port increments pin data by 1 and latches it to output increments output latch contents by 1 incs @hl latch set1 <1> rewrites output latch contents of specified bit as changes status of output pin as specified by clr1 <1> specified by instruction. however, output latch instruction mov1 <1> , cy contents of other bits are undefined sktclr <1> remark <1> : indicates two addressing modes: portn, bit and portn.@l. instruction executed
chapter 5 peripheral hardware function 84 user s manual u10201ej2v4um00 5.1.5 connecting pull-up resistor each port pin of the pd753036 can be connected with a pull-up resistor (except the p00 and bp0 through bp7 pins). some pins can be connected with a pull-up resistor via software and the others can be connected by mask option. table 5-4 shows how to specify the connection of the pull-up resistor to each port pin. the pull-up resistor is connected via software in the format shown in fig. 5-8. the pull-up resistor can be connected only to the pins of ports 3 and 6 in the input mode. when the pins are set in the output mode, the pull-up resistor cannot be connected regardless of the setting of poga, pogb. table 5-4 specifying connection of pull-up resistor port (pin name) specifying connection of pull-up resistor specified bit port 0 (p01-p03) note connected internal pull-up resistor in 3-bit units via software poga.0 port 1 (p10-p13) connected internal pull-up resistor in 4-bit units via software poga.1 port 2 (p20-p23) poga.2 port 3 (p30-p33) poga.3 port 6 (p60-p63) poga.6 port 7 (p70-p73) poga.7 port 8 (p80-p83) pogb.0 port 4 (p40-p43) connected in 1-bit units by mask option port 5 (p50-p53) note p00 pin cannot be connected with a pull-up resistor. remark the port pins of the pd75p3036 are not connected with the pull-up resistor by the mask option, and are always open.
chapter 5 peripheral hardware function 85 user s manual u10201ej2v4um00 pull-up resistor specification register group b fig. 5-8 format of pull-up resistor register specification 0 does not connect internal pull-up resistor 1 connects internal pull-up resistor pull-up resistor register group a 765432 10 po0 po1 po3 po2 _ _ po6 po7 address poga fdch symbol port 0 (p01-p03) port 1 (p10-p13) port 2 (p20-p23) port 3 (p30-p33) port 6 (p60-p63) port 7 (p70-p73) 765432 10 po8 _ __ _ _ _ _ address pogb fdeh symbol port 8 (p80-p83)
chapter 5 peripheral hardware function 86 user s manual u10201ej2v4um00 5.1.6 i/o timing of digital i/o port fig. 5-9 shows the timing at which data is output to the output latch and the timing at which the pin data or the data of the output latch is loaded to the internal bus. fig. 5-10 shows the on timing when a pull-up resistor is connected to a port pin via software. fig. 5-9 i/o timing of digital i/o port (a) when data is loaded by 1-machine cycle instruction (b) when data is loaded by 2-machine cycle instruction (c) when data is latched by 1-machine cycle instruction (d) when data is latched by 2-machine cycle instruction instruction execution input timing 2 machine cycles manipulation instruction instruction execution manipulation instruction 1 machine cycle input timing instruction execution manipulation instruction 3 0 1 output latch (output pin) instruction execution 0 1 output latch (output pin) manipulation instruction
chapter 5 peripheral hardware function 87 user s manual u10201ej2v4um00 fig. 5-10 on timing of pull-up resistor connected via software instruction execution pull-up resistor register pull-up resistor setting instruction 2 machine cycles
chapter 5 peripheral hardware function 88 user s manual u10201ej2v4um00 5.2 clock generation circuit the clock generation circuit supplies various clocks to the cpu and peripheral hardware units and controls the operation mode of the cpu. 5.2.1 configuration of clock generation circuit fig. 5-11 shows the configuration of the clock generation circuit. fig. 5-11 block diagram of clock generation circuit note instruction execution remarks 1. f x = main system clock frequency 2. f xt = subsystem clock frequency 3. = cpu clock 4. pcc: processor clock control register 5. scc: system clock control register 6. one clock cycle (t cy ) of is one machine cycle of an instruction. wait release signal from bt internal bus scc0 scc3 pcc0 pcc1 halt note pcc3 pcc stop note pcc2 clears pcc2, pcc3 xt1 xt2 subsystem clock oscillation circuit x1 x2 main system clock oscillation circuit oscillation stops selector 1/1 to 1/4096 divider circuit lcd controller/driver watch timer . basic interval timer (bt) . timer/event counter . serial interface . watch timer . lcd controller/driver . a/d converter . int0 noise rejection circuit . clock output circuit s rq q r s stop f/f halt f/f 1/4 divider circuit . cpu . int0 noise rejection circuit . clock output circuit standby release signal from interrupt control circuit reset signal 4 scc selector 1/2 1/4 1/16 v dd v dd f x f xt wm.3
chapter 5 peripheral hardware function 89 user s manual u10201ej2v4um00 5.2.2 function and operation of clock generation circuit the clock generation circuit generates the following types of clocks and controls the operation mode of the cpu in the standby mode: main system clock f x subsystem clock f xt cpu clock clock to peripheral hardware the operation of the clock generation circuit is determined by the processor clock control register (pcc) and system clock control register (scc), as follows: (a) when the reset signal is asserted, the slowest mode of the main system clock (10.7 s at 6.0 mhz) is selected (pcc = 0, scc = 0). (b) the cpu clock can be changed in four steps (0.67, 1.33, 2.67, or 10.7 s at 6.0 mhz) by pcc with the main system clock selected. (c) two standby modes, stop and halt, can be used with the main system clock selected. (d) ultra low-speed, power-saving (122 ms at 32.768 khz) can be performed with the subsystem clock selected by scc. in this case, the value set for pcc has no influence on the cpu clock. (e) the oscillation of the main system clock can be stopped by scc when the subsystem clock has been selected. moreover, the halt mode can be used. however, the stop mode cannot be used. (the oscillation of the subsystem clock cannot be stopped.) (f) the main system clock is divided and supplied to the peripheral hardware units. the subsystem clock can be directly supplied only to the watch timer. therefore, the watch function, and the lcd controller and buzzer output function that operate on the clock supplied from the watch timer can continue their operations even in the standby mode. (g) the watch timer and lcd controller can continue their operations when the subsystem clock has been selected. the serial interface and timer/event counter can continue operation when an external clock has been used as the clock. the other hardware units, however, operate on the main system clock and therefore, cannot be used when the main system clock is stopped.
chapter 5 peripheral hardware function 90 user s manual u10201ej2v4um00 (1) processor clock control register (pcc) pcc is a 4-bit register that selects the cpu clock with the lower 2 bits and controls the cpu operation mode with the higher 2 bits (refer to fig. 5-12 ). when either bit 3 or 2 of this register is set to 1 , the standby mode is set. when the standby mode has been released by the standby release signal, both the bits are automatically cleared and the normal operation mode is set (for details, refer to chapter 7 standby function ). the lower 2 bits of pcc are set by a 4-bit memory manipulation instruction (clear the higher 2 bits to 0 ). bits 3 and 2 are set to 1 by the stop and halt instructions, respectively. the stop and halt instructions can always be executed regardless of the contents of mbe. the cpu clock can be selected only when the processor operates with the main system clock. when the subsystem clock is used, the lower 2 bits of pcc are invalid, and the clock frequency is fixed to f xt /4. the stop instruction can be executed only when the processor operates with the main system clock. examples 1. to set the fastest mode of machine cycle (0.67 s at 6.0 mhz) sel mb15 mov a, #0011b mov pcc, a 2. to set the machine cycle to 1.63 s (f x = 4.19 mhz) sel mb15 mov a, #0010b mov pcc, a 3. to set stop mode (be sure to write nop instruction after stop and halt instructions) stop nop pcc is cleared to 0 when the reset signal is asserted.
chapter 5 peripheral hardware function 91 user s manual u10201ej2v4um00 fig. 5-12 format of processor clock control register 3210 cpu clock select bit pcc0 pcc1 pcc2 pcc3 address pcc fb3h symbol (f x = 6.0 mhz) scc3, scc0 = 00 ( ): f x = 6.0mhz cpu clock frequency i machine cycle 0 = f x /64 (93.7 khz) 0 10.7 s 0 = f x /16 (375 khz) 1 2.67 s 1 = f x /8 (750 khz) 0 1.33 s 1 = f x /4 (1.5 mhz) 1 0.67 s scc3, scc0 = 01 or 11 ( ): f xt = 32,768 khz cpu clock frequency 1 machine cycle = f xt /4 (8.192 khz) 122 s (f x = 4.19 mhz) scc3, scc0 = 00 ( ): f x = 4.19 mhz cpu clock frequency i machine cycle 0 = f x /64 (65.5 khz) 0 15.3 s 0 = f x /16 (261.8 khz) 1 3.81 s 1 = f x /8 (524 khz) 0 1.91 s 1 = f x /4 (1.05 mhz) 1 0.95 s scc3, scc0 = 01 or 11 ( ): f xt : 32.768 khz cpu clock frequency 1 machine cycle = f xt /4 (8.192 khz) 122 s remarks cpu operation mode control bit 0 normal operation mode 0 0 halt mode 1 1 stop mode 0 1 setting prohibited 1 1. f x : main system clock oscillation circuit output frequency 2. f xt : subsystem clock oscillation circuit output frequency
chapter 5 peripheral hardware function 92 user s manual u10201ej2v4um00 (2) system clock control register (scc) scc is a 4-bit register that selects cpu clock with its least significant bit and controls oscillation of the main system clock with the most significant bit (refer to fig. 5-13 ). although bits 0 and 3 of scc exist at the same data memory address, both the bits cannot be changed at the same time. to set bits 0 and 3 of scc, therefore, use a bit manipulation instruction. bits 0 and 3 of scc can be always manipulated regardless of the content of mbe. oscillation of the main system clock can be stopped by setting bit 3 of scc only when the processor operates with the subsystem clock. to stop oscillation of the main system clock, use the stop instruction scc is cleared to 0 when the reset signal is asserted. fig. 5-13 format of system clock control register cautions 1. it takes up to 1/f xt to change the system clock. to stop oscillation of the main system clock, therefore, set scc.3 to 1 after the subsystem clock has been selected and the number of machine cycles shown in table 5-5 has elapsed. 2. the stop mode cannot be set even if the oscillation is stopped by setting scc.3 when the processor operates with the main system clock. 3. do not set scc.0 to ??when pcc = 0001b ( = f x /16). to change the system clock from the main to sub, set pcc in the other way (pcc 0001b). do not set pcc = 0001b while the processor operates with the subsystem clock. 4. when scc.3 is set to ?? the x1 input pin is internally short-circuited to v ss (ground potential) to suppress the leakage of the crystal oscillation circuit. to use an external clock as the main system clock, therefore, do not set scc.3 to ?? 3210 scc3 cpu clock selection scc0 _ _ scc3 address scc fb7h symbol scc0 main system clock oscillation 0 main system clock 0 can oscillate 0 subsystem clock 1 1 setting prohibited 0 1 subsystem clock 1 oscillation stopped
chapter 5 peripheral hardware function 93 user s manual u10201ej2v4um00 (3) system clock oscillation circuit (i) the main system clock oscillation circuit is oscillated by the crystal or ceramic resonator connected across the x1 and x2 pins (4.194304 mhz typ.). an external clock can also be input. fig. 5-14 external circuit of main system clock oscillation circuit (a) crystal or ceramic oscillation (b) external clock caution the stop mode cannot be set when an external clock is input because the x1 pin is internally short-circuited to v ss in the stop mode. (ii) the subsystem clock oscillation circuit is oscillated by the crystal resonator (32.768 khz typ.) connected across the xt1 and xt2 pins. an external clock can also be input. fig. 5-15 external circuit of subsystem clock oscillation circuit (a) crystal oscillation (b) external clock x1 x2 crystal resonator or ceramic resonator pd753036 pd753036 x1 x2 v dd v dd external clock xt1 xt2 v dd pd753036 externai clock pd753036 xt1 xt2 32.768 khz v dd
chapter 5 peripheral hardware function 94 user s manual u10201ej2v4um00 cautions 1. wire the portion enclosed by the dotted line in figs. 5-14 and 5-15 as follows to prevent adverse influence by wiring capacitance when using the main system clock and subsystem clock oscillation circuits. keep the wiring length as short as possible. do not cross the wiring with any other signal lines. do not route the wiring in the vicinity of any line through which a high alternating current is flowing. always keep the potential at the connecting point of the capacitor of the oscillation circuit at the same level as v dd . do not connect the wiring to a ground pattern through which a high current is flowing. do not extract signals from the oscillation circuit. the amplification factor of the subsystem clock oscillation circuit is kept low to reduce the power consumption. therefore, this is more susceptible to noise than the main system clock oscillation circuit. to use the subsystem clock oscillation circuit, therefore, you should exercise care with the wiring. fig. 5-16 shows incorrect examples of connecting the resonator. fig. 5-16 incorrect example of connecting resonator (1/2) (a) wiring length too long (b) crossed signal line remark when using the subsystem clock, take x1 and x2 in the above figures as xt1 and xt2. also, connect a resistor in series with xt2. pd753036 x1 x2 v dd v dd pd753036 x1 x2 v dd v dd portn (n = 0-8)
chapter 5 peripheral hardware function 95 user s manual u10201ej2v4um00 fig. 5-16 incorrect example of connecting resonator (2/2) (c) high alternating current close to signal line (d) current flowing through power line of oscillation circuit (potential at points a, b, and c changes) (e) signal extracted (f) main system clock and subsystem clock signal lines close and in parallel with each other remark when using the subsystem clock, assume x1 and x2 in the above figures as xt1 and xt2. also, connect a resistor in series with xt2. pd753036 high current x1 x2 v dd v dd pd753036 x1 x2 v dd high current pnm v dd c b a v dd pd753036 xt1 xt2 v dd v dd x1 x2 xt2 and x1 are wired in parallel pd753036 x1 x2 v dd v dd
chapter 5 peripheral hardware function 96 user s manual u10201ej2v4um00 caution 2. in fig. 5-16(f), xt2 and x1 are wired in parallel. in consequence, the cross-talk noise of x1 may be superimposed on xt2, causing malfunctioning. to prevent this, connect the ic pin in between the xt2 and x1 pins to vdd. (4) divider circuit the divider circuit divides the output of the main system clock oscillation circuit (f x ) to generate various clocks. pd753036 xt1 xt2 v dd x1 x2 v dd ic
chapter 5 peripheral hardware function 97 user s manual u10201ej2v4um00 (5) control function of subsystem clock oscillation circuit the subsystem clock oscillation circuit of the pd753036 has the following two control functions: function to select whether the internal feedback resistor is used or not, via software note function to decrease the drive current of the internal inverter to suppress the current consumption when the operating voltage is high (v dd 2.7 v) each function can be used by setting or resetting the bits 0 and 1 of the suboscillation circuit control register (sos) (refer to fig. 5-17 ). fig. 5-17 subsystem clock oscillation circuit note when not using the subsystem clock, power supply current can be reduced by selecting sos.0 = 1 (internal feedback resistor not used) when a stop instruction is executed. (6) suboscillation circuit control register (sos) the sos register selects whether the internal feedback resistor is used or not, and controls the drive current of the internal inverter (refer to fig. 5-18 ). when the reset signal is asserted, all the bits of this register are cleared to 0. the function of each flag of the sos register is described below. v dd xt1 xt2 sos.1 inverter sos.0 feedback resistor pd753036
chapter 5 peripheral hardware function 98 user s manual u10201ej2v4um00 (a) sos.0 (feedback resistor cut flag) with the pd753036, it can be selected via software by changing the status of sos.0 whether the internal feedback resistor is used. if sos.0 is set to 1 when the resonator is not used, the feedback circuit is turned off. therefore, current consumption can be reduced. when using the resonator, be sure to reset sos.0 to 0 (to turn on the feedback circuit). (b) sos.1 (drive capability select flag) the internal inverter of the subsystem clock oscillation circuit of the pd753036 has a high drive current so that the inverter can operate on a low voltage (v dd = 1.8 v). if the supply voltage is high (v dd 2.7 v), therefore, the supply current increases. in this case, set sos.1 to 1 to decrease the drive current of the inverter and thereby to reduce the supply current. if sos.1 is set to 1 when v dd is less than 2.7 v, oscillation may be stopped because the drive current runs short. therefore, be sure to reset sos.1 to 0 when v dd is less than 2.7 v. fig. 5-18 format of suboscillation circuit control register (sos) remark when the subsystem clock is not necessary, set the xt1 and xt2 pins and sos register as follows: xt1 : connect to v ss or v dd xt2 : open sos : 0001b 32 address 10 sos sos0 fcfh sos1 00 symbol suboscillation circuit feedback resistor cut flag be sure to reset bits 2 and 3 of sos to 0. 0 uses internal feedback resistor 1 does not use internal feedback resistor suboscillation circuit current cut flag 0 high drive current (1.8 v v dd ) 1 low drive current (2.7 v v dd )
chapter 5 peripheral hardware function 99 user? manual u10201ej2v4um00 scc0 pcc1 pcc0 5.2.3 setting system clock and cpu clock (1) time required to select system clock and cpu clock the system clock and cpu clock can be selected by using the least significant bit of scc and the lower 2 bits of pcc. the processor does not operate with the selected clock, however, immediately after data has been written to the registers, for the duration of specific machine cycles. to stop oscillation of the main system clock, therefore, execute the stop instruction or set the bit 3 of scc after a specific time has elapsed. table 5-5 maximum time required to select system clock and cpu clock set value before selection set value after selection scc0 pcc1 pcc0 scc0 pcc1 pcc0 scc0 pcc1 pcc0 scc0 pcc1 pcc0 scc0 pcc1 pcc0 0 0 0 1 machine cycle 1 machine cycle 1 machine cycle f x machine cycle (3 machine cycles) 0 1 4 machine cycles 4 machine cycles 4 machine cycles f x machine cycle (11 machine cycles) 1 0 8 machine cycles 8 machine cycles 8 machine cycles f x machine cycle (23 machine cycles) 1 1 16 machine cycles 16 machine cycles 16 machine cycles f x machine cycle (46 machine cycles) 1 x x 1 machine cycle setting prohibited 1 machine cycle 1 machine cycle cautions 1. do not set scc.0 to ??when pcc = 0001b ( = f x /16). before changing the system clock from main to sub, set pcc to the other values (pcc 0001b). when the processor operates with the subsystem clock, do not set pcc = 0001b. 2. the values of f x and f xt change depending on the ambient temperature of the resonators and variations in the performance of load capacitance. especially, if f x is higher than the nominal value, or f xt is lower than the nominal value, the number of machine cycles calculated by expressions f x /64f xt , f x /16f xt , f x /8f xt , and f x /4f xt in the above table will be greater than the number of machine cycles calculated with the nominal values of f x and f xt . to set the wait time necessary for selecting the cpu clock, therefore, use the number of machine cycles greater than that calculated with the nominal values of f x and f xt . remarks 1. ( ): f x = 6.0 mhz, f xt = 32.768 khz 2. x: don? care 3. the cpu clock is supplied to the internal cpu and its inverse number (defined to be 1 machine cycle in this manual) is the minimum instruction execution time. 64f xt 8f xt 4f xt 0000010100111 16f xt
chapter 5 peripheral hardware function 100 user? manual u10201ej2v4um00 (2) procedure to select system clock and cpu clock fig. 5-19 illustrates the procedure to select the system clock and cpu clock. fig. 5-19 selecting system clock and cpu clock <1> when the reset signal is asserted, wait time note during which oscillation is stabilized elapses. the cpu then starts operating at the slowest speed of the system clock (10.7 s at 6.0 mhz, 15.3 s at 4.19 mhz). <2> after the time during which the voltage on the v dd pin rises to the sufficient level at which the cpu can operate at the highest speed has elapsed, the contents of pcc are rewritten, and the cpu operates at the highest speed. <3> when the commercial power source is turned off, it is detected by an interrupt (use of int4 is effective). bit 0 of scc is set to ?? and the cpu operates with the subsystem clock (at this time, oscillation of the subsystem clock must be started in advance). after the time required to change the system clock from the main to sub (46 machine cycles) has elapsed, set bit 3 of scc to ??to stop oscillation of the main system clock. <4> when the commercial power source is turned back on again, it is detected by an interrupt. clear bit 3 of scc to ??to start oscillation of the main system clock. after the time necessary for the oscillation to become stabilized has elapsed,clear bit 0 of scc to ?? this means that the cpu can operate at the highest speed. note can be selected from 2 15 /f x and 2 17 /f x by mask option. 2 15 /f x 5.46 ms: at 6.0 mhz, 7.81 ms: at 4.19 mhz 2 17 /f x 21.8 ms: at 6.0 mhz, 31.3 ms: at 4.19 mhz however, the wait time is fixed to 2 15 /f x because the pd75p3036 has no mask option. on off commercial power source voltage on v dd pin reset signal system clock cpu clock internal reset operation f x = 6.0mhz f xt = 32.768khz f x wait note f x f xt f xt 10.7 s 0.67 s 122 s 0.67 s
chapter 5 peripheral hardware function 101 user s manual u10201ej2v4um00 5.2.4 clock output circuit (1) configuration of clock output circuit fig. 5-20 shows the configuration of the clock output circuit. (2) function of clock output circuit the clock output circuit outputs a clock pulse from the p22/pcl/pto2 pin and is used to supply a remote control output or a clock pulse to a peripheral lsi. the clock pulse is output in the following procedure: (a) select the clock output frequency. disable clock output. (b) write 0 to the output latch of p22. (c) set port 2 in the output mode. (d) disable timer/event counter (channel 2) output. (e) enable clock output. fig. 5-20 block diagram of clock output circuit remark the circuit has been designed so that a pulse with short width is not output when clock output is enabled or disabled. from clock generation circuit fx/2 3 fx/2 4 fx/2 6 selector clom3 clom1 clom0 clom 0 p22 output latch port2.2 4 internal bus port 2 l/o mode specification bit bit 2 of pmgb output buffer pcl/p22/pto2 selector timer/event counter (channel 2)
chapter 5 peripheral hardware function 102 user s manual u10201ej2v4um00 (3) clock output mode register (clom) clom is a 4-bit register that controls clock output. this register is set by a 4-bit memory manipulation instruction. clom cannot be read. example to output cpu clock from pcl/p22/pto2 pin sel mb15 ; or clr1 mbe mov a, #1000b mov clom, a when the reset signal is asserted, clom is cleared to 0 , and clock output is disabled. fig. 5-21 format of clock output mode register caution be sure to clear bit 2 of clom to 0. 32 address 10 0 output note (1.5mhz, 750 khz, 375 khz, 93.8 khz) clom clom0 fd0h clom1 clom3 0 symbol fx = 6.0 mhz 0 0 f x /2 3 output (750 khz) 1 1 f x /2 4 output (375 khz) 0 1 f x /2 6 output (93.8 khz) 1 clock output frequency select bit 0 disables output clock output enable/disable bit 1 enables output 0 output note (1.05 mhz, 524 khz, 262 khz, 65.5 khz) fx = 4.19 mhz 0 0 f x /2 3 output (524 khz) 1 1 f x /2 4 output (262 khz) 0 1 f x /2 6 output (65.5 khz) 1 note is the cpu clock selected by pcc.
chapter 5 peripheral hardware function 103 user s manual u10201ej2v4um00 (4) application example of remote controller output the clock output function of the pd753036 can be used for remote controller output. the carrier frequency of the remote controller output is selected by the clock frequency select bit of the clock output mode register. output of the pulse is enabled or disabled by controlling the clock output enable/disable bit via software. the circuit has been designed so that a pulse with a narrow width is not output when clock output is enabled or disabled. fig. 5-22 application example of remote controller output clom bit 3 pcl pin output
chapter 5 peripheral hardware function 104 user s manual u10201ej2v4um00 5.3 basic interval timer/watchdog timer the pd753036 has an 8-bit basic interval timer/watchdog timer that has the following functions: (a) interval timer operation to generate reference time interrupt (b) watchdog timer operation to detect program hang-up and reset cpu (c) to select and count wait time when standby mode is released (d) to read count value 5.3.1 configuration of basic interval timer/watchdog timer fig. 5-23 shows the configuration of the basic interval timer/watchdog timer. fig. 5-23 block diagram of basic interval timer/watchdog timer note instruction execution fx/2 5 fx/2 7 fx/2 9 fx/2 12 mpx from clock generation circuit btm3 btm2 btm1 btm0 3 4 basic interval timer (8-bit divider circuit) internal bus 8 btm set1 note 1 wdtm bt bt interrupt request flag clear wait release signal when standby mode is released clear internal reset signal set1 note set vectored interrupt request signal irqbt
chapter 5 peripheral hardware function 105 user s manual u10201ej2v4um00 5.3.2 basic interval timer mode register (btm) btm is a 4-bit register that controls the operation of the basic interval timer (bt). this register is set by a 4-bit memory manipulation instruction. bit 3 of bt can be manipulated by a bit manipulation instruction. example to set interrupt generation interval to 1.37 ms (6.0 mhz) sel mb15 ; or clr1 mbe clr1 wdtm mov a, #1111b mov btm,a ; btm 1111b when bit 3 of this register is set to 1 , the contents of bt are cleared, and at the same time, the basic interval timer/watchdog timer interrupt request flag (irqbt) is cleared (the basic interval timer/watchdog timer is started). when the reset signal is asserted, the contents of this register are cleared to 0 , and the generation interval time of the interrupt request signal is set to the longest value.
chapter 5 peripheral hardware function 106 user s manual u10201ej2v4um00 fig. 5-24 format of basic interval timer mode register 3210 btm0 btm1 btm2 btm3 address btm f85h symbol f x = 6.0 mhz specifies input clock f x /2 12 (1.46 khz) 0 f x /2 9 (11.7 khz) 1 1 f x /2 7 (46.9 khz) 0 1 f x /2 5 (188 khz) 1 others setting prohibited interrupt interval time (wait time when standby mode is released) f x = 4.19 mhz basic interval timer/watchdog timer start control bit when "1" is written to this bit, the basic interval timer/watchdog timer is started (counter and interrupt request flag are cleared). when the timer starts operating, this bit is automatically reset to "0". 1 1 1 00 0 2 20 /f x (175 ms) 2 17 /f x (21.8 ms) 2 15 /f x (5.46 ms) 2 13 /f x (1.37 ms) _ specifies input clock f x /2 12 (1.02 khz) 0 f x /2 9 (8.18 khz) 1 1 f x /2 7 (32.768 khz) 0 1 f x /2 5 (131 khz) 1 others setting prohibited interrupt interval time (wait time when standby mode is released) 1 1 1 00 0 2 20 /f x (250 ms) 2 17 /f x (31.3 ms) 2 15 /f x (7.81 ms) 2 13 /f x (1.95 ms) _
chapter 5 peripheral hardware function 107 user s manual u10201ej2v4um00 5.3.3 watchdog timer enable flag (wdtm) wdtm is a flag that enables assertion of the reset signal when a overflow occurs. this flag is set by a bit manipulation instruction. once this flag has been set, it cannot be cleared by an instruction. example to set watchdog timer function sel mb15 ; or clr1 mbe set1 wdtm set1 btm.3 ; sets bit 3 of btm to 1 the content of this flag is cleared to 0 when the reset signal is asserted. fig. 5-25 format of watchdog timer enable flag (wdtm) 5.3.4 operation as basic interval timer when wdtm is reset to 0 , the interrupt request flag (irqbt) is set by the overflow of the basic interval timer (bt), and the basic interval timer/watchdog timer operates as the basic interval timer. bt is always incremented by the clock supplied by the clock generation circuit and its counting operation cannot be stopped. four time intervals at which the interrupt occurs can be selected by btm (refer to fig. 5-24 ). by setting bit 3 of btm to 1 , bt and irqbt can be cleared (command to start the interval timer). the count value of bt can be read by using an 8-bit manipulation instruction. no data can be written to bt. start the timer operation as follows (<1> and <2> may be performed simultaneously): <1> set interval time to btm. <2> set bit 3 of btm to 1 . example to generate interrupt at intervals of 1.37 ms (at 6.0 mhz) set1 mbe sel mb15 mov a, #1111b mov btm, a ; sets time and starts ei ; enables interrupt ei iebt ; enables bt interrupt wdtm 0 bt mode sets irqbt when basic interval timer (bt) overflows address f8bh.3 1 wt mode asserts internal reset signal when basic interval timer (bt) overflows
chapter 5 peripheral hardware function 108 user s manual u10201ej2v4um00 5.3.5 operation as watchdog timer the basic interval timer/watchdog timer operates as a watchdog timer that asserts the internal reset signal when an overflow occurs in the basic interval timer (bt), if wdtm is set to 1 . however, if the overflow occurs during the oscillation wait time that elapses after the stop instruction has been released, the reset signal is not asserted. (once wdtm has been set to 1 , it cannot be cleared by any means other than reset.) bt is always incremented by the clock supplied from the clock generation circuit, and its count operation cannot be stopped. in the watchdog timer mode, a program hang-up is detected by using the interval time at which bt overflows. as this interval time, four values can be selected by using bits 2 through 0 of btm (refer to fig. 5-24 ). select the interval time best-suited to detecting any hang-up that may occur in you system. set an interval time, divide the program into several modules that can be executed within the set interval time, and execute an instruction that clears bt at the end of each module. if this instruction that clears bt is not executed within the set interval time (in other words, if a module of the program is not normally executed, i.e., if a hang up occurs), bt overflows, the internal reset signal is asserted, and the program is terminated forcibly. consequently, asserting of the internal reset signal indicates occurrence and detection of a program hang-up. set the watchdog timer as follows (<1> and <2> may be performed simultaneously): <1> set interval time to btm. <2> set bit 3 of btm to 1 . <3> set wdtm to 1 . <4> after setting <1> through <3> above, set bit 3 of btm to 1 within the interval time. initial setting
chapter 5 peripheral hardware function 109 user s manual u10201ej2v4um00 example to use the basic interval timer/watchdog timer as a watchdog timer with a time interval of 5.46 ms (at 6.0 mhz). divide the program into several modules, each of which is completed within the set time of btm (5.46 ms), and clear bt at the end of each module. if a hang-up occurs, bt is not cleared within the set time. as a result, bt overflows, and the internal reset signal is asserted. (after that, set bit 3 of btm to 1 every 5.46 ms.) initial setting: set1 sel mov mov set1 . . . mbe mb15 a, #1101b btm, a wdtm ; sets time and starts ; enables watchdog timer module 1: . . . . . . set1 sel set1 mbe mb15 btm.3 processing completed within 5.46 ms module 2: . . . . . . set1 sel set1 mbe mb15 btm.3 processing completed within 5.46 ms . . .
chapter 5 peripheral hardware function 110 user s manual u10201ej2v4um00 5.3.6 other functions the basic interval timer/watchdog timer has the following functions, regardless of the operations as the basic interval timer or watchdog timer: <1> selects and counts wait time after standby mode has been released <2> reads count value (1) selecting and counting wait time after stop mode has been released when the stop mode has been released, a wait time elapses during which the operation of the cpu is stopped until the basic interval timer (bt) overflows, so that oscillation of the system clock becomes stabilized. the wait time that elapses after the reset signal has been asserted is fixed by the mask option. when the stop mode is released by an interrupt, however, the wait time can be selected by btm. the wait time in this case is the same as the interval time shown in fig. 5-24. set btm before setting the stop mode (for details, refer to chapter 7 standby function ). example to set a wait time of 5.46 ms that elapses when the stop mode has been released by an interrupt (at 6.0 mhz) set1 mbe sel mb15 mov a, #1101b mov btm, a ; sets time stop ; sets stop mode nop (2) reading count value the count value of the basic interval timer (bt) can be read by using an 8-bit manipulation instruction. no data can be written to the basic interval timer. caution to read the count value of bt, execute the read instruction two times to prevent undefined data from being read while the count value is updated. compare the two read values. if the values are similar, take the latter value as the result. if the two values are completely different, redo from the beginning.
chapter 5 peripheral hardware function 111 user s manual u10201ej2v4um00 examples 1. to read count value of bt set1 mbe sel mb15 mov hl, #bt ; sets address of bt to hl loop: mov xa, @hl ; reads first time mov bc, xa mov xa, @hl ; reads second time ske xa, bc br loop 2. to set a high-level width of a pulse input to int4 interrupt (detected at both the edges) (the pulse width must not exceed the set value of bt, and the set value of btm is 5.46 ms or longer (at 6.0 mhz))
chapter 5 peripheral hardware function 112 user? manual u10201ej2v4um00 5.4 watch timer the pd753036 is provided with one channel of watch timer. this watch timer has the following functions: (a) sets a test flag (irqw) at time intervals of 0.5 second. irqw can be used to release the standby mode. (b) can generate the time intervals of 0.5 second from both the main system clock and subsystem clock. use a main clock frequency f x of 4.194304 mhz and a subsystem clock frequency of f xt of 32.768 khz. (c) can increase the time interval 128-fold (3.91 ms) in the fast forward mode. this is useful for debugging and testing the program. (d) can output any frequency (2.048, 4.096, or 32.768 khz) to the p23/buz pin to active a buzzer or trim the system clock oscillation frequency. (e) can start the watch from zero second by clearing the divider circuit.
chapter 5 peripheral hardware function 113 user? manual u10201ej2v4um00 5.4.1 configuration of watch timer fig. 5-26 shows the configuration of the watch timer. fig. 5-26 block diagram of watch timer 8 internal bus clear divider circuit wm p23/buz f x 128 (32.768 khz) f xt (32.768 khz) f w f w 2 7 (256 hz : 3.91 ms) f w 2 14 2 hz 0.5 sec p23 output latch output buffer intw irqw set signal port2.3 bit 2 of pmgb from clock generation circuit selector selector (32.768 khz) 4 khz 2 khz f w 2 3 f w 2 4 f w 2 6 (512 hz : 1.95 ms) selector port 2 i/o mode bit test instruction wm7 0 wm5 wm4 wm3 wm2 wm1 wm0 f lcd ( ) : f x = 4.194304 mhz, f xt = 32.768 khz
chapter 5 peripheral hardware function 114 user s manual u10201ej2v4um00 5.4.2 watch mode register the watch mode register (wm) is an 8-bit register that controls the watch timer. fig. 5-27 shows the format of this register. all the bits of wm, except bit 3, are set by an 8-bit manipulation instruction. bit 3 is used to test the input level of the xt1 pin. no data can be written to this bit. all the bits, except bit 3, are cleared to 0 when the reset signal is asserted. example to generate time interval from the main system clock (4.19 mhz) with the buzzer output enabled clr1 mbe mov xa, #84h mov wm, xa ; sets wm
chapter 5 peripheral hardware function 115 user s manual u10201ej2v4um00 fig. 5-27 format of watch mode register 765432 10 buz output enable/disable bit wm0 wm1 wm3 wm2 wm4 wm5 0 wm7 address wm f98h symbol wm7 disables buz output 0 enables buz output 1 buz output frequency select bit wm5 buz output frequency wm4 (2.048 khz) 0 0 1 0 1 setting prohibited 0 f w (32.768 khz) 1 1 f w 2 4 (4.096 khz) f w 2 3 input level of xt1 pin (bit test only can be tested) wm3 input to xt1 pin is low 0 input to xt1 pinis high 1 watch operation enable/disable bit wm2 stops watch operation (clears divider circuit) 0 enables watch operation 1 operation mode select bit wm1 normal watch mode (f w /2 14 : sets irqw at 0.5-second intervals) 0 fast forward watch mode (f w /2 7 : sets irqw at 3.91-ms intervals) 1 count clock (f w ) select bit wm0 selects system clock division output: f x /128 0 selects subsystem clock: f xt 1 remark ( ): f w = 32.768 khz
chapter 5 peripheral hardware function 116 user s manual u10201ej2v4um00 5.5 timer/event counter the pd753036 is provided with three channels of timers/event counters. the timers/event counters have the following functions: (a) programmable interval timer operation (b) outputs square wave of any frequency to pton pin (c) event counter operation (d) divides tin pin input by n and outputs to pton pin (divider circuit operation) (e) supplies serial shift clock to serial interface circuit (f) count status call function the timers/event counters can operate in the following four modes selected by the corresponding mode registers. table 5-6 operation modes channel channel 0 channel 1 channel 2 mode 8-bit timer/event counter mode gate control function note pwm pulse generator mode 16-bit timer/event counter mode gate control function note carrier generator mode note this function is used to generate a gate control signal. 5.5.1 configuration of timer/event counter figs. 5-28 through 5-30 show the configuration of the timers/event counters.
chapter 5 peripheral hardware function 117 user s manual u10201ej2v4um00 fig. 5-28 block diagram of timer/event counter (channel 0) note execution of the instruction _ tm06 tm05 tm04 tm03 tm02 _ _ tm0 8 internal bus 8 8 modulo register (8) port1.3 mpx from clock generation circuit p13/ti0 input buffer set1 note tmod0 8 comparator (8) 8 count regjster (8) t0 cp clear timer operation starts tout f/f reset coincidence to enable flag toe0 p20 output latch port2.0 port 2 i/o mode bit 2 of pmgb p20/pto0 to serial interface output buffer intt0 lrqt0 set signal irqt0 c]ear signal reset to timer/event counter (channel 2) tout0
chapter 5 peripheral hardware function 118 user s manual u10201ej2v4um00 fig. 5-29 block diagram of timer/event counter (channel 1) 8 internal bus tm16 _ tm15 tm14 tm13 tm12 tm11 tm10 tm1 port1.2 input buffer p80/ti1 timer/event counter (channel 2) output from clock generation circuit mpx decoder 8 modulo register (8) 8 tmod1 comparator (8) 8 count register (8) t1 cp clear reset irqt1 clear signal reset selector int1 lrqt1 set signal timer/event counter (channel 2) comparator (in 16-bit timer/event counter mode) timer/event counter (channel 2) coincidence signal (in 16-bit timer/event counter mode) timer/event counter (channel 2) reload signal t1 enable flag toe1 p21 output latch port2.1 port 2 l/o mode bit 2 of pmgb p21/pto1 output buffer coincidence timer operation starts 16-bit timer/event counter mode tout f/f
chapter 5 peripheral hardware function 119 user s manual u10201ej2v4um00 fig. 5-30 block diagram of timer/event counter (channel 2) 8 internal bus _ tm26 tm25 tm24 tm23 tm22 tm21 tm20 p80/ti2 port1.2 input buffer from clock generation circuit mpx decoder 8 high-level period setting modulo register (8) 8 8 modulo register (8) 8 mpx (8) 8 comparator (8) count register (8) 8 tout f/f clear irqt2 c]ear signal intt2(lrqt2 set signal) tmod2h tmod2 reset 8 tgce ___ toe2 remc nrzb nrz tc2 selector selector p22 output latch port2.2 port 2 l/o mode p22/pcl/pto2 timer/event counter (channel 1) clock input bit 2 of pmgb 16-bit timer/event counter mode timer operation starts timer/event counter (channel 0) tout f/f timer/event counter (channel 1) coincidence signal (in 16-bit timer/event counter mode) timer/event counter (channel 1) clear signal (in 16-bit timer/ counter mode) timer/event counter (channel 1) coincidence signal (in carrier generator mode) coincidence reset re- load overflow carrier generator mode output buffer tm2 cp selector from clock output circuit
chapter 5 peripheral hardware function 120 user s manual u10201ej2v4um00 (1) timer/event counter mode registers (tm0, tm1, tm2) a mode register (tmn) is an 8-bit register that controls the corresponding timer/event counter. figs. 5-31 through 5-33 show the formats of the various mode registers. the timer/event counter mode register is set by an 8-bit memory manipulation instruction. bit 3 of this register is a timer start bit and can be manipulated in 1-bit units independently of the other bits. this bit is automatically reset to 0 when the timer starts operating. all the bits of the timer/event counter mode register are cleared to 0 when the reset signal is asserted. examples 1. to start timer in interval timer mode of cp = 5.86 khz (at 6.0 mhz) sel mb15 ; or clr1 mbe mov xa, #01001100b mov tmn, xa ; tmn 4ch 2. to restart timer according to setting of timer/event counter mode register sel mb15 ; or clr1 mbe set1 tmn.3 ; tmn.bit3 1
chapter 5 peripheral hardware function 121 user s manual u10201ej2v4um00 fig. 5-31 format of timer/event counter mode register (channel 0) 765432 10 f x = 6.0 mhz _ _ tm03 tm02 tm04 tm05 tm06 _ address tm0 fa0h symbol count pulse (cp) select bit tm06 count pulse (cp) tm05 0 0 0 0 1 f x /2 10 (5.86 khz) 0 f x /2 8 (23.4 khz) 0 1 rising edge of ti0 falling edge of ti0 1 1 1 f x /2 4 (375 khz) 1 setting prohibited f x /2 6 (93.8 khz) others tm04 0 1 0 1 0 1 f x = 4.19 mhz tm06 count pulse (cp) tm05 0 0 0 0 1 f x /2 10 (4.09 khz) 0 f x /2 8 (16.4 khz) 0 1 rising edge of ti0 falling edge of ti0 1 1 1 f x /2 4 (262 khz) 1 setting prohibited f x /2 6 (65.5 khz) others tm04 0 1 0 1 0 1 tm03 clears counter and irqt0 flag when "1" is written. starts count operation if bit 2 is set to "1". timer start command bit operation mode tm02 0 1 stops (count value retained) count operation count operation
chapter 5 peripheral hardware function 122 user s manual u10201ej2v4um00 fig. 5-32 format of timer/event counter mode register (channel 1) 765432 10 f x = 6.0 mhz tm10 tm11 tm13 tm12 tm14 tm15 tm16 _ address tm1 fa8h symbol count pulse (cp) select bit tm16 count pulse (cp) tm15 0 0 0 0 0 overflow of timer/event counter channel 2 1 f x /2 5 (187 khz) 1 0 rising edge of ti1 falling edge of ti1 0 1 1 f x /2 10 (5.86 khz) 0 f x /2 8 (23.4 khz) f x /2 12 (1.46 khz) tm14 0 1 0 1 0 1 tm13 clears counter and irqt1 flag when "1" is written. starts count operation if bit 2 is set to "1". timer start command bit operation mode tm12 0 1 stops (count value retained) count operation count operation 110 f x /2 6 (93.8 khz) 111 f x = 4.19 mhz tm16 count pulse (cp) tm15 0 0 0 0 0 overflow of timer/event counter channel 2 1 f x /2 5 (131 khz) 1 0 rising edge of ti1 falling edge of ti1 0 1 1 f x /2 10 (4.09 khz) 0 f x /2 8 (16.4 khz) f x /2 12 (1.02 khz) tm14 0 1 0 1 0 1 110 f x /2 6 (65.5 khz) 111 operation mode select bit tm11 count pulse (cp) tm10 0 0 0 1 others setting prohibited 8-bit timer/event counter mode note 16-bit timer/event counter mode note this mode is used as a carrier generator mode when used in combination with tm20, tm21 (=11) of timer/event counter mode register (channel 2).
chapter 5 peripheral hardware function 123 user s manual u10201ej2v4um00 fig. 5-33 format of timer/event counter mode register (channel 2) 765432 10 f x = 6.0 mhz tm20 tm21 tm23 tm22 tm24 tm25 tm26 _ address tm2 f90h symbol count pulse (cp) select bit tm26 count pulse (cp) tm25 0 0 0 0 0 f x /2 (3.00 mhz) 1 f x (6.00 mhz) 1 0 rising edge of ti2 falling edge of ti2 0 1 1 f x /2 8 (23.4 khz) 0 f x /2 6 (93.8 khz) f x /2 10 (5.86 khz) tm24 0 1 0 1 0 1 tm23 clears counter and irqt2 flag when "1" is written. starts count operation if bit 2 is set to "1". timer start command bit operation mode tm22 0 1 stops (count value retained) count operation count operation 110 f x /2 4 (375 khz) 111 f x = 4.19 mhz tm26 count pulse (cp) tm25 0 0 0 0 0 f x /2 (2.10 mhz) 1 f x (4.19 mhz) 1 0 rising edge of ti2 falling edge of ti2 0 1 1 f x /2 8 (16.4 khz) 0 f x /2 6 (65.5 khz) f x /2 10 (4.09 khz) tm24 0 1 0 1 0 1 110 f x /2 4 (262 khz) 111 operation mode select bit tm21 mode tm20 0 0 1 0 1 16-bit timer/event counter mode 0 carrier generator mode 1 1 8-bit timer/event counter mode pwm pulse generator mode
chapter 5 peripheral hardware function 124 user s manual u10201ej2v4um00 (2) timer/event counter output enable flags (toe0, toe1) timer/event counter output enable flags toe0 and toe1 enable or disable output to the pto0 and pto1 pins in the timer out f/f (tout f/f) status. the timer out f/f is inverted by a coincidence signal from the comparator. when bit 3 of timer/event counter mode register tm0 or tm1 is set to 1 , the timer out f/f is cleared to 0 . toe0, toe1, and timer out f/f are cleared to 0 when the reset signal is asserted. fig. 5-34 format of timer/event counter output enable flag toe0 address fa2h channel 0 toe1 faah channel 1 0 disabled 1 enabled timer/event counter output enable flag (w)
chapter 5 peripheral hardware function 125 user s manual u10201ej2v4um00 (3) timer/event counter control register (tc2) the timer/event counter control register (tc2) is an 8-bit register that controls the timer/event counter. fig. 5-35 shows the format of this register. tc2 is set by an 8- or 4-bit manipulation instruction and bit manipulation instruction. all the bits of tc2 are cleared to 0 when the internal reset signal is asserted. fig. 5-35 format of timer/event counter control register 765432 10 gate control enable flag nrz nrzb toe2 remc _ _ _ tgce address tc2 f92h symbol tgce gate control 0 disabled (timer/event counter performs count operation regardless of status of sampling clock if bit 2 of tm2 is set to "1".) no return zero flag nrz 0 1 outputs low level outputs carrier pulse or high level no return zero data 1 enabled (timer/event counter performs count operation when sampling clock is high if bit 2 of tm2 is set to "1", and stops count operation when sampling clock is low.) timer output enable flag toe2 0 1 disabled (low level output) enabled timer output remote controller output control flag remc 0 1 outputs carrier pulse when nrz = 1 outputs high level when nrz = 1 remote controller output no return zero buffer flag nrzb no return zero data to be output next. transferred to nrz when interrupt of timer/event counter (channel 1) occurs
chapter 5 peripheral hardware function 126 user s manual u10201ej2v4um00 5.5.2 operation in 8-bit timer/even counter mode in this mode, a timer/event counter is used as an 8-bit timer/event counter. in this case, the timer/event counter operates as an 8-bit programmable interval timer or event counter. (1) register setting in the 8-bit timer/event counter mode, the following four registers are used: timer/event counter mode register (tmn) timer/event counter control register (tc2) note timer/event counter count register (tn) timer/event counter modulo register (tmodn) note channels 0 and 1 of the timer/event counter use the timer/event counter output enable flags (toe0 and toe1). (a) timer/event counter mode register (tmn) in the 8-bit timer/event counter mode, set tmn as shown in fig. 5-36 (for the format of tmn, refer to figs. 5-31 through 5-33). tmn is manipulated by an 8-bit manipulation instruction. bit 3 is a timer start command bit which can be manipulated in 1-bit units. this bit is automatically cleared to 0 when the timer starts operating. tmn is cleared to 00h when the internal reset signal is asserted.
chapter 5 peripheral hardware function 127 user s manual u10201ej2v4um00 fig. 5-36 setting of timer/event counter mode register (1/3) (a) timer/event counter (channel 0) 765432 10 count pulse (cp) select bit _ _ tm03 tm02 tm04 tm05 tm06 _ address tm0 fa0h symbol tm06 count pulse (cp) tm05 0 0 0 0 1 f x /2 10 0 f x /2 8 0 1 rising edge of ti0 falling edge of ti0 1 1 1 f x /2 4 1 setting prohibited f x /2 6 others tm04 0 1 0 1 0 1 tm03 clears counter and irqt0 flag when "1" is written. starts count operation if bit 2 is set to "1". timer start command bit operation mode tm02 0 1 stops (count value retained) count operation count operation
chapter 5 peripheral hardware function 128 user s manual u10201ej2v4um00 fig. 5-36 setting of timer/event counter mode register (2/3) (b) timer/event counter (channel 1) 765432 10 tm10 tm11 tm13 tm12 tm14 tm15 tm16 _ address tm1 fa8h symbol tm13 clears counter and irqt1 flag when "1" is written. starts count operation if bit 2 is set to "1". timer start command bit operation mode tm12 0 1 stops (count value retained) count operation count operation count pulse (cp) select bit tm16 count pulse (cp) tm15 0 0 0 0 0 overflow of timer/event counter channel 2 1 f x /2 5 1 0 rising edge of ti1 falling edge of ti1 0 1 1 f x /2 10 0 f x /2 8 f x /2 12 tm14 0 1 0 1 0 1 110 f x /2 6 111 operation mode select bit tm11 0 8-bit timer/event counter mode mode tm10 0
chapter 5 peripheral hardware function 129 user s manual u10201ej2v4um00 fig. 5-36 setting of timer/event counter mode register (3/3) (c) timer/event counter (channel 2) 765432 10 tm20 tm21 tm23 tm22 tm24 tm25 tm26 address tm2 f90h symbol tm23 clears counter and irqt2 flag when "1" is written. starts count operation if bit 2 is set to "1". timer start command bit operation mode tm22 0 1 stops (count value retained) count operation count operation count pulse (cp) select bit tm26 count pulse (cp) tm25 0 0 0 0 0 f x /2 1 f x 1 0 rising edge of ti2 falling edge of ti2 0 1 1 f x /2 8 0 f x /2 6 f x /2 10 tm24 0 1 0 1 0 1 110 f x /2 4 111 operation mode select bit tm21 0 8-bit timer/event counter mode mode tm20 0
chapter 5 peripheral hardware function 130 user s manual u10201ej2v4um00 (b) timer/event counter control register (tc2) in the 8-bit timer/event counter mode, set tc2 as shown in fig. 5-37 (for the format of tc2, refer to fig. 5-35 format of timer/event counter control register ). tc2 is manipulated by an 8- or 4-bit, or bit manipulation instruction. the value of tc2 is cleared to 00h when the internal reset signal is asserted. the flags shown in a solid line in the figure below are used in the 8-bit timer/event counter mode. do not use the flags shown by a dotted line in the figure below in the 8-bit timer/event counter mode (clear these flags to 0). fig. 5-37 setting of timer/event counter control register fig. 5-38 setting of timer/event counter output enable flag 765432 10 gate control enable flag nrz nrzb toe2 remc _ _ _ tgce tc2 symbol tgce gate control 0 disabled (timer/event counter performs count operation regardless of status of sampling clock if bit 2 of tm2 is set to "1".) 1 enabled (timer/event counter performs count operation when sampling clock is high if bit 2 of tm2 is set to "1", and stops count operation when sampling clock is low.) timer output enable flag toe2 0 1 disabled (low level output) enabled timer output toe0 address fa2h channel 0 toe1 faah channel 1 0 disabled (low level output) 1 enabled timer/event counter output enable flag (w)
chapter 5 peripheral hardware function 131 user s manual u10201ej2v4um00 (2) time setting of timer/event counter [timer set time] (cycle) is calculated by dividing the [contents of modulo register + 1] by the [count pulse (cp) frequency] selected by the mode register. t (sec) = = (n+1) (resolution) where, t (sec) : timer set time (seconds) f cp (hz) : cp frequency (hz) n : contents of modulo register (n 0) once the timer has been set, interrupt request flag irqtn is set at the set time interval of the timer. table 5-7 shows the resolution of each count pulse of the timer/event counter and the longest set time (time when ffh is set to the modulo register). table 5-7 resolution and longest set time (1/2) (a) timer/event counter (channel 0) mode register at 6.0 mhz at 4.19 mhz tm06 tm05 tm04 resolution longest set time resolution longest set time 1 0 0 171 s 43.7 ms 244 s 62.5 ms 1 0 1 42.7 s 10.9 ms 61.0 s 15.6 ms 1 1 0 10.7 s 2.73 ms 15.3 s 3.91 ms 1 1 1 2.67 s 683 s 3.82 s 977 s (b) timer/event counter (channel 1) mode register at 6.0 mhz at 4.19 mhz tm16 tm15 tm14 resolution longest set time resolution longest set time 0 1 1 5.33 s 1.37 ms 7.64 s 1.95 ms 1 0 0 683 s 175 ms 980 s 250 ms 1 0 1 171 s 43.7 ms 244 s 62.5 ms 1 1 0 42.7 s 10.9 ms 61.0 s 15.6 ms 1 1 1 10.7 s 2.73 ms 15.3 s 3.91 s n +1 f cp .
chapter 5 peripheral hardware function 132 user s manual u10201ej2v4um00 table 5-7 resolution and longest set time (2/2) (c) timer/event counter (channel 2) mode register at 6.0 mhz at 4.19 mhz tm26 tm25 tm24 resolution longest set time resolution longest set time 0 1 0 333 ns 85.3 s 477 ns 122 s 0 1 1 167 ns 42.7 s 239 ns 61.1 s 1 0 0 171 s 43.7 ms 244 s 62.5 ms 1 0 1 42.7 s 10.9 ms 61.0 s 15.6 ms 1 1 0 10.7 s 2.73 ms 15.3 s 3.91 ms 1 1 1 2.67 s 683 s 3.82 s 977 s (3) timer/event counter operation the timer/event counter operates as follows. to perform this operation, clear the gate control enable flag (tgce) of the timer/event counter control register (tc2) to 0. fig. 5-39 shows the configuration when the timer/event counter operates. <1> the count pulse (cp) is selected by the mode register (tmn) and is input to the count register (tn). <2> the contents of tn are compared with those of the modulo register (tmodn). when the contents of these registers coincide, a coincidence signal is generated, and the interrupt request flag (irqtn) is set. at the same time, the timer out flip/flop (tout f/f) is inverted. fig. 5-40 shows the timing of the timer/event counter operation. the timer/event counter operation is usually started in the following procedure: <1> set the number of counts to tmodn. <2> sets the operation mode, count pulse, and start command to tmn. caution set a value other than 00h to the modulo register (tmodn). to use the timer/event counter output pin (pton), set the p2n pin as follows: <1> clear the output latch of p2n. <2> set port 2 in the output mode. <3> disconnect the pull-up resistor from port 2. (when output pto2, disable pcl output.) <4> set the timer/event counter output enable flag (toen) to 1.
chapter 5 peripheral hardware function 133 user s manual u10201ej2v4um00 fig. 5-39 configuration when timer/event counter operates note the signal output to the serial interface can be output only by channel 0 of the timer/event counter. fig. 5-40 count operation timing mpx tin internal clock modulo register (tmodn) comparator count register (tn) cp tout f/f pton coincidence clear inttn (lrqtn set signal) to serial interface note count pulse (cp) modulo register (tmodn) count register (tn) tout f/f 01 2 n _ 1n 0 1 2 n _ 1n01234 n coincidence coincidence reset timer start command
chapter 5 peripheral hardware function 134 user s manual u10201ej2v4um00 (4) event counter operation with gate control function (8 bits) the timer/event counter (channel 2) can be used as an event counter possessing a gate control function. when this function is used, set the gate control enable flag (tgce) of the timer/event counter control register to 1. when the timer/event counter channel 0 counts to the specified number, the gate signal is generated. when the gate signal (output of tout f/f of t0) is high, the count pulse of the timer/event counter (channel 2) can be counted as shown in fig. 5-42 (for details, refer to (3) timer/event counter operation ). <1> the count pulse (cp) is selected by the mode register (tm2) and cp is input to the count register (t2) when the gate signal is high. <2> an interrupt occurs at the rising and falling edges of the gate signal. usually, the contents of t2 are read by the subroutine of the interrupt that occurs at the falling edge and t2 is cleared to prepare for the next count operation. fig. 5-42 shows the timing of the event counter operation. the event counter operation is usually started in the following procedure: <1> set the operation mode, count pulse, and counter clear command to tm2. <2> set the number of counts to tmod0. <3> set the operation mode, count pulse, and start command to tm0. caution set a value other than 00h to the modulo registers (tmod0 and tmod2).
chapter 5 peripheral hardware function 135 user s manual u10201ej2v4um00 fig. 5-41 configuration when event counter operates fig. 5-42 timing of event counter operation mpx ti0 internal clock modulo register (tmod0) comparator count register (t0) cp tout f/f pto0 coincidence clear intt0 (lrqt0 set signal) mpx ti2 internal clock modulo register (tmod2) comparator count register (t2) cp tout f/f pto2 coincidence clear intt2 (lrqt2 set signal) count pulse (cp) modulo register (tmod0) count register (t0) gate signal (tout f/f) event input (tl2) count register (t2) 01 2 n _ 1n 0 1 2 n _ 1n01234 n counting disabled counting enabled coincidence coincidence reset counting disabled irqt0 set irqt0 set 012n _ 2n _ 1n timer start command counter clear command
chapter 5 peripheral hardware function 136 user s manual u10201ej2v4um00 (5) application of 8-bit timer/event counter mode (a) as an interval timer that generates an interrupt at 50-ms intervals set the higher 4 bits of the mode register (tmn) to 0100b, and select 62.3 ms (f x = 4.19 mhz) as the longest set time. set the lower 4 bits of tmn to 1100b. the set value of the modulo register (tmodn) is as follows: = 205 cdh
chapter 5 peripheral hardware function 137 user s manual u10201ej2v4um00 (c) as an event counter that performs measurement in the sampling period (15 ms) and hold period (2 ms) after a disable period of 121 s set the timer/event counter (channel 0) as follows: set the higher 4 bits of the mode register (tm0) to 0101b and select 15.6 ms as the longest set time. set the lower 4 bits of tm0 to 1100b, select the 8-bit timer/event counter mode and count operation, and issue the timer start command. set the modulo register (tmod0) to 01h (121 s) the first time, and then to 20h (15.03 ms) and f5h (2.02 ms). set the timer/event counter (channel 2) as follows: set the higher 4 bits of tm2 to 0000b and select the ti2 rising edge. set the lower 4 bits of tm2 to 1100b, and select the 8-bit timer/counter mode and count operation, and issue the counter clear command. set tgce to 1 to enable gate control. set the maximum set value ffh to tmod2. specify mem as the memory that stores the contents of the count register (t2).
chapter 5 peripheral hardware function 138 user s manual u10201ej2v4um00 ;
chapter 5 peripheral hardware function 139 user s manual u10201ej2v4um00 5.5.3 operation in pwm pulse generator mode (pwm mode) in the pwm mode, the timer/event counter operates as an 8-bit pwm pulse generator. (1) register setting in the pwm mode, the following five registers are used: timer/event counter mode register (tm2) timer/event counter control register (tc2) timer/event counter count register (t2) timer/event counter high-level period setting modulo register (tmod2h) timer/event counter modulo register (tmod2) (a) timer/event counter mode register (tm2) in the pwm mode, set tm2 as shown in fig. 5-43 (for the format of tm2, refer to fig. 5-33 format of timer/event counter mode register (channel 2) ). tm2 is manipulated by an 8-bit manipulation instruction. bit 3 is a timer start command bit which can be manipulated in 1-bit units and is automatically cleared to 0 when the timer starts operating. tm2 is also cleared to 00h when the internal reset signal is asserted.
chapter 5 peripheral hardware function 140 user s manual u10201ej2v4um00 fig. 5-43 setting of timer/event counter mode register 765432 10 tm20 tm21 tm23 tm22 tm24 tm25 tm26 _ address tm2 f90h symbol tm23 clears counter and irqt2 flag when "1" is written. starts count operation if bit 2 is set to "1". timer start command bit operation mode tm22 0 1 stops (count value retained) count operation count operation count pulse (cp) select bit tm26 count pulse (cp) tm25 0 0 0 0 01 1 0 rising edge of ti2 falling edge of ti2 0 1 10 tm24 0 1 0 1 0 1 110 111 operation mode select bit tm21 0 pwm pulse generator mode mode tm20 1 f x /2 f x f x /2 8 f x /2 6 f x /2 10 f x /2 4
chapter 5 peripheral hardware function 141 user s manual u10201ej2v4um00 (b) timer/event counter control register (tc2) in the pwm mode, set tc2 as shown in fig. 5-44 (for the format of tc2, refer to fig. 5-35 format of timer/event counter control register) . tc2 is manipulated by an 8-, 4-, or bit manipulation instruction. tc2 is cleared to 00h when the internal reset signal is asserted. the flags shown by a solid line in the figure below are used in the pwm mode. do not use the flags shown by a dotted line in the pwm mode (clear these flags to 0). fig. 5-44 setting of timer/event counter control register 765432 10 nrz nrzb toe2 remc _ _ _ tgce tc2 symbol timer output enable flag toe2 0 1 disabled (low level output) enabled timer output
chapter 5 peripheral hardware function 142 user s manual u10201ej2v4um00 (2) pwm pulse generator operation the pwm pulse generator operation is performed as follows. fig. 5-45 shows the configuration of the timer/ event counter in the pwm pulse generator mode. <1> a count pulse (cp) is selected by the mode register (tm2), and is input to the count register (t2). <2> the contents of t2 are compared with those of the high-level period setting modulo register (tmod2h). if the contents of the two registers coincide, a coincidence signal is generated, and the timer output flip-flop (tout f/f) is inverted. <3> the contents of t2 are compared with those of the modulo register (tmod2). when the contents of the two registers coincide, a coincidence signal is generated, and an interrupt request flag (irqt2) is set. at the same time, tout f/f is inverted. <4> the operations <2> and <3> are alternately repeated. fig. 5-46 shows the timing of the pwm pulse generator operation. the pwm pulse generator operation is usually started in the following procedure: <1> set the number of counts to tmod2h. <2> sets the number of low levels to tmod2. <3> set an operation mode, count pulse, and start command to tm2. caution set a value other than 00h to the modulo register (tmod2) and high-level period setting modulo register (tmod2h). to use the timer/event counter output pin (pto2), set the p22 pin as follows: <1> clear the output latch of p22. <2> set port 2 in the output mode. <3> disconnect the pull-up resistor from port 2, and disable pcl output. <4> set the timer/event counter output enable flag (toe2) to 1. fig. 5-45 configuration in pwm pulse generator operation mpx ti2 internal clock mpx comparator count register (t2) cp tout f/f pto2 coincidence clear intt2 (lrqt2 set signal) high-level period setting modulo register (tmod2h) modulo register (tmod2)
chapter 5 peripheral hardware function 143 user s manual u10201ej2v4um00 fig. 5-46 timing of pwm pulse generator operation count pulse (cp) modulo register (tmod2) count register (t2) tout f/f 01 2 m _ 1m 0 1 2 n _ 1n01234 n coincidence coincidence reset timer start command high-level period setting modulo register (tmod2h) m irqt2 set
chapter 5 peripheral hardware function 144 user s manual u10201ej2v4um00 (3) application of pwm mode to output a pulse with a frequency of 38.0 khz (cycle of 26.3 s) and a duty factor of 1/3 to the pto2 pin set the higher 4 bits of the mode register (tm2) to 0011b and select 61.1 s (at 4.19 mhz) as the longest set time. set the lower 4 bits of tm2 to 1101b, and select the pwm mode and count operation, and issue the timer start command. set the timer output enable flag (toe2) to 1 to enable timer output. set the high-level period setting modulo register (tmod2h) as follows: 1 = 36.7 1 36 = 24h the set value of the modulo register (tmod2) is as follows: 1 = 73.4 1 72 = 48h
chapter 5 peripheral hardware function 145 user? manual u10201ej2v4um00 5.5.4 operation in 16-bit timer/event counter mode in this mode, two timer/event counter channels, 1 and 2, are used in combination to implement 16-bit programmable interval timer or event timer operation. (1) register setting in the 16-bit timer/event counter mode, the following seven registers are used: timer/event counter mode registers tm1 and tm2 timer/event counter control register tc2 note timer/event count registers t1 and t2 timer/event count modulo registers tmod1 and tmo2 note timer/event counter channel 1 uses the timer/event counter output enable flag (toe1). (a) timer/event counter mode registers (tm1 and tm2) in the 16-bit timer/event counter mode, tm1 and tm2 are set as shown in fig. 5-47 (for the formats of tm1 and tm2, refer to fig. 5-32 format of timer/event counter mode register (channel 1) and fig. 5-33 format of timer/event counter mode register (channel 2) ). tm1 and tm2 are manipulated by an 8-bit manipulation instruction. bit 3 of these registers is a timer start command bit that can be manipulated in 1-bit units and is automatically cleared to 0 when the timer starts operating. tm1 and tm2 are cleared to 00h when the internal reset signal is asserted. the flags shown by a solid line in fig. 5-46 are used in the 16-bit timer/event counter mode. do not use the flags shown by a dotted line in the 16-bit timer/event counter mode (clear these flags to 0).
chapter 5 peripheral hardware function 146 user? manual u10201ej2v4um00 fig. 5-47 setting of timer/event counter mode registers tm20 tm21 tm23 tm22 tm24 tm25 tm26 _ tm2 f90h tm23 clears counter and irqtn flag when "1" is written. starts count operation if bit 2 is set to "1". timer start command bit operation mode tm22 0 1 stops (count value retained) count operation count operation count pulse (cp) select bit tmn6 tm1 tmn5 0 0 0 0 0 overflow of count register (t2) 1 f x 2 5 1 0 rising edge of ti1 falling edge of ti1 0 1 1 f x /2 10 0 f x /2 8 f x /2 12 tmn4 0 1 0 1 0 1 110 f x /2 6 111 operation mode select bit tm21 1 16-bit timer/event counter mode mode tm20 0 765432 10 tm10 tm11 tm13 tm12 tm14 tm15 tm16 _ address tm1 fa8h symbol tm2 rising edge of ti2 falling edge of ti2 f x /2 f x f x /2 8 f x /2 6 f x /2 10 f x /2 4 tm11 1 tm10 0
chapter 5 peripheral hardware function 147 user s manual u10201ej2v4um00 (b) timer/event counter control register (tc2) in the 16-bit timer/event counter mode, set tc2 as shown in fig. 5-48 (for the format of tc2, refer to fig. 5-35 format of timer/event counter control register ). tc2 is manipulated by an 8-, 4-, or bit manipulation instruction. tc2 is cleared to 00h when the internal reset signal is asserted. the flags shown by a solid line in fig. 5-47 are used in the 16-bit timer/event counter mode. do not use the flags shown by a dotted line in the 16-bit timer/event counter mode (clear these flags to 0). fig. 5-48 setting of timer/event counter control register 765432 10 gate control enable flag nrz nrzb toe2 remc _ _ _ tgce tc2 symbol tgce gate control 0 disabled (timer/event counter performs count operation regardless of status of sampling clock if bit 2 of tm2 is set to "1".) 1 enabled (timer/event counter performs count operation when sampling clock is high if bit 2 of tm2 is set to "1". and stops count operation when sampling clock is low.) timer output enable flag toe2 0 1 disabled (low level output) enabled timer output
chapter 5 peripheral hardware function 148 user s manual u10201ej2v4um00 (2) time setting of timer/event counter [timer set time] (cycle) is calculated by dividing the [contents of modulo register + 1] by the [count pulse (cp) frequency] selected by the mode register. t (sec) = = (n+1) (resolution) where, t (sec) : timer set time (seconds) f cp (hz) : cp frequency (hz) n : contents of modulo register (n 0) once the timer has been set, interrupt request flag irqt2 is set at the set time interval of the timer. table 5-8 shows the resolution of each count pulse of the timer/event counter and the longest set time (time when ffh is set to the modulo register). table 5-8 resolution and longest set time (a) timer/event counter (channel 1) mode register at 6.0 mhz at 4.19 mhz tm16 tm15 tm14 resolution longest set time resolution longest set time 0 1 1 5.33 s 350 ms 7.64 s 500 ms 1 0 0 683 s 44.7 s 980 s 64.3 s 1 0 1 171 s 11.2 s 244 s 16.0 ms 1 1 0 42.7 s 2.80 s 61.0 s 4.0 ms 1 1 1 10.7 s 699 ms 15.3 s 1.0 s (b) timer/event counter (channel 2) mode register at 6.0 mhz at 4.19 mhz tm26 tm25 tm24 resolution longest set time resolution longest set time 0 1 0 333 ns 21.8 ms 477 ns 31.2 ms 0 1 1 167 ns 10.9 ms 239 ns 15.6 ms 1 0 0 171 s 11.2 s 244 s 16.0 s 1 0 1 42.7 s 2.80 s 61.0 s 4.0 s 1 1 0 10.7 s 699 ms 15.3 s 1.0 s 1 1 1 2.67 s 175 ms 3.82 s 250 ms n+1 f cp .
chapter 5 peripheral hardware function 149 user s manual u10201ej2v4um00 (3) timer/event counter operation the timer/event counter operates as follows. to perform this operation, clear the gate control enable flag (tgce) of the timer/event counter control register (tc2) to 0. fig. 5-49 shows the configuration when the timer/event counter operates. <1> the count pulse (cp) is selected by the mode registers tm1 and tm2 and is input to count register t2. the overflow of t2 is input to count register t1. <2> the contents of t1 are compared with those of modulo register tmod1. when the contents of these registers coincide, a coincidence signal is generated. <3> the contents of t2 are compared with those of modulo register tmod2. when the contents of these registers coincide, a coincidence signal is generated. <4> if the coincidence signals in <2> and <3> overlap, interrupt request flag irqt2 is set. at the same time, timer out flip-flop tout f/f is inverted. fig. 5-50 shows the operation timing of the timer/event counter operation. the timer/event counter operation is usually started by the following procedure: <1> set the higher 8 bits of the number of counts 16 bits wide to tmod1. <2> set the lower 8 bits of the number of counts 16 bits wide to tmod2. <3> set the count pulse to tm1. <4> set the operation mode, count pulse, and start command to tm2. caution set a value other than 00h to the modulo register (tmod2). to use timer/event counter output pin pto2, set the p22 pin as follows: <1> clear the output latch of p22. <2> set port 2 in the output mode. <3> disconnect the pull-up resistor from port 2, and disable pcl output. <4> set timer/event counter output enable flag toe2 to 1.
chapter 5 peripheral hardware function 150 user s manual u10201ej2v4um00 fig. 5-49 configuration when timer/event counter operates mpx ti1 internal clock modulo register (tmod1) comparator count register (t1) cp mpx ti2 internal clock modulo register (tmod2) comparator count register (t2) cp tout f/f pto2 intt2 (lrqt2 set signal) clear coincidence coincidence clear count pulse (cp) modulo register (tmod2) count register (t2) count register (t1) tout f/f 0 1 2 n 255 0 1 n _ 1n 0 1 2 n set timer start command 2 modulo register (tmod1) m 0m _ 1m 0 coincidence coincidence fig. 5-50 timing of count operation
chapter 5 peripheral hardware function 151 user s manual u10201ej2v4um00 (4) event counter operation with gate control function (16 bits) the timer/event counter channels 1 and 2 can be used as an event counter having a gate control function. when this function is used, set the gate control enable flag (tgce) of the timer/event counter control register to 1. when the timer/event counter channel 0 counts to the specified number, the gate signal is generated. when the gate signal (output of tout f/f of t0) is high, the count pulse of the timer/event counter channel 1 and 2 can be counted as shown in fig. 5-52 (for details, refer to (3) timer/event counter operation ). <1> the count pulse (cp) is selected by mode registers tm1 and tm2, and cp is input to count register (t2) when the gate signal is high. the overflow of t2 is input to count register t1. <2> an interrupt occurs at the rising and falling edges of the gate signal. usually, the contents of t1 and t2 are read by the subroutine of the interrupt that occurs at the falling edge and t1 and t2 are cleared to prepare for the next count operation. fig. 5-52 shows the timing of the event counter operation. the event counter operation is usually started in the following procedure: <1> set the operation mode and count pulse to tm1. <2> set the operation mode, count pulse, and counter clear command to tm2. <3> set the number of counts to tmod0. <4> set the operation mode, count pulse, and start command to tm0. cautions 1. set a value other than 00h to the modulo registers (tmod0, tmod1, and tmo2). 2. do not set the timer/event counter interrupt enable flag (iet1) to 1.
chapter 5 peripheral hardware function 152 user s manual u10201ej2v4um00 fig. 5-51 configuration when event counter operates mpx ti0 internal clock modulo register (tmod0) comparator count register (t0) cp tout f/f pto0 coincidence clear intt0 (lrqt0 set signal) mpx ti2 internal clock modulo register (tmod2) comparator count register (t2) cp tout f/f pto2 coincidence clear intt2 (lrqt2 set signal) mpx ti1 modulo register (tmod1) comparator count register (t1) cp coincidence clear internal clock
chapter 5 peripheral hardware function 153 user s manual u10201ej2v4um00 fig. 5-52 timing of event counter operation count pulse (cp) modulo register (tmod0) count register (t0) gate signal (tout f/f) event input (tl2) count register (t1: high) 01 2 n _ 1n 0 1 2 n _ 1n01234 n counting disabled counting enabled coincidence coincidence reset counting disabled irqt0 set irqt0 set 0i timer start command counter clear command count register (t2: low) 012j _ 2j _ 1j
chapter 5 peripheral hardware function 154 user s manual u10201ej2v4um00 (5) application of 16-bit timer/event counter mode (a) as an interval timer that generates an interrupt at 5-sec intervals set the higher 4 bits of the mode register (tm1) to 0010b, and select the overflow of count register (t2). set the higher 4 bits of tm2 to 0100b and select 16.0 sec (at 4.19 mhz) as the longest set time. set the lower 4 bits of tm1 to 0010b and select the 16-bit timer/counter mode. set the lower 4 bits of tm2 to 1110b, select the 16-bit timer/counter mode and count operation. then, issue the timer start command. the set values of the modulo registers (tmod1 and tmod2) are as follows: = 20491.8 1 500bh
chapter 5 peripheral hardware function 155 user s manual u10201ej2v4um00 (b) to generate interrupt when the number of pulses input from the ti2 pin reaches 1000 (pulse is high-active) set the higher 4 bits of the mode register (tm1) to 0010b and select the overflow of the count register (t2). set the higher 4 bits of tm2 to 0000b and select the rising edge of the ti2 input. set the lower 4 bits of tm1 to 0010b and select the 16-bit timer/event counter mode. set the lower 4 bits of tm2 to 1110b, select the 16-bit timer/event counter mode and count operation. then, issue the timer start command. the set value of the modulo registers (tmod1 and tmod2) is 1000 1 = 999 = 03e7h. set 03h to tmod1 and e7h to tmod2.
chapter 5 peripheral hardware function 156 user s manual u10201ej2v4um00 (c) as an event counter that performs measurement in the sampling period (15 ms) and hold period (2 ms) after a disable period of 121 s set the timer/event counter (channel 0) as follows: set the higher 4 bits of the mode register (tm0) to 01010b and select 15.6 ms (at 4.19 mhz) as the longest set time. set the lower 4 bits of tm0 to 1100b, select the 8-bit timer/event counter mode and count operation. then, issue the timer start command. set the modulo register (tmod0) to 01h (121 s) the first time, and then to 20h (15.03 ms) and f5h (2.02 ms). set the timer/event counter (channel 1) as follows: set the higher 4 bits of tm1 to 0010b and select the overflow of the count register (t2). set the lower 4 bits of tm0 to 0010b, and select the 16-bit timer/counter mode and count operation. then, issue the timer start command. set the maximum set value ffh to tmod1. specify mem1 as the memory that stores the contents of the count register (t1). set the timer/event counter (channel 2) as follows: set the higher 4 bits of tm2 to 0000b and select the rising edge of ti2. set the lower 4 bits of tm2 to 1110b, and select the 16-bit timer/counter mode and count operation. then, issue the counter clear command. set tgce to 1 to enable gate control. set the maximum set value ffh to tmod2. specify mem2 as the memory that stores the contents of the count register (t2).
chapter 5 peripheral hardware function 157 user s manual u10201ej2v4um00
chapter 5 peripheral hardware function 158 user s manual u10201ej2v4um00 5.5.5 operation in carrier generator mode (cg mode) in the pwm mode, timer/event counter channels 1 and 2 operate in combination to implement an 8-bit carrier generator operation. when using cg mode, use it in combination with channel 1 and channel 2 of timer/event counter. timer/event counter channel 1 generates a remote controller signal. timer/event counter channel 2 generates a carrier clock. (1) register setting in the cg mode, the following eight registers are used: timer/event counter mode registers tm1 and tm2 timer/event counter control register tc2 note timer/event counter count registers t1 and t2 timer/event counter modulo registers tmod1 and tmod2 timer/event counter high-level period setting modulo register tmod2h note timer/event counter channel 1 uses the timer/event counter output enable flag (toe1). (a) timer/event counter mode registers (tm1 and tm2) in the cg mode, set tm1 and tm2 as shown in fig. 5-53 (for the formats of tm1 and tm2, refer to fig. 5-32 format of timer/event counter mode register (channel 1) and fig. 5-33 format of timer/event counter mode register (channel 2) ). tm1 and tm2 are manipulated by an 8-bit manipulation instruction. bit 3 of tm1 and tm2 is timer start command bit which can be manipulated in 1-bit units and is automatically cleared to 0 when the timer starts operating. tm1 and tm2 are also cleared to 00h when the internal reset signal is asserted.
chapter 5 peripheral hardware function 159 user s manual u10201ej2v4um00 fig. 5-53 setting of timer/event counter mode register (n = 1, 2) tm20 tm21 tm23 tm22 tm24 tm25 tm26 _ tm2 f90h tmn3 clears counter and irqtn flag when "1" is written. starts count operation if bit 2 is set to "1". timer start command bit operation mode tmn2 0 1 stops (count value retained) count operation count operation count pulse (cp) select bit tmn6 tm1 tmn5 0 0 0 0 0 carrier clock input 1 f x 2 5 1 0 rising edge of ti1 falling edge of ti1 0 1 1 f x /2 10 0 f x /2 8 f x /2 12 tmn4 0 1 0 1 0 1 110 f x /2 6 111 operation mode select bit tm21 1 carrier generator mode mode tm20 1 765432 10 tm10 tm11 tm13 tm12 tm14 tm15 tm16 _ address tm1 fa8h symbol tm2 rising edge of ti2 falling edge of ti2 f x /2 f x f x /2 8 f x /2 6 f x /2 10 f x /2 4 tm11 0 tm10 0
chapter 5 peripheral hardware function 160 user s manual u10201ej2v4um00 (b) timer/event counter control register (tc2) in the cg mode, set the timer output enable flag (toe1) and tc2 as shown in fig. 5-54 (for the format of tc2, refer to fig. 5-35 format of timer/event counter control register ). toe1 is manipulated by a bit manipulation instruction. tc2 is manipulated by an 8-, 4-, or bit manipulation instruction. toe1 and tc2 are cleared to 00h when the internal reset signal is asserted. the flags shown by a solid line in the figure below are used in the cg mode. do not use the flags shown by a dotted line in the cg mode (clear these flags to 0). fig. 5-54 setting of timer/event counter output enable flag fig. 5-55 setting of timer/event counter control register address toe1 faah 0 disabled 1 enabled timer/event counter output enable flag (w) _ tgce nrzb no return zero data to be output next. transferred to nrz when timer /event counter (channel 1) interrupt occurs no return zero buffer flag no return zero flag nrz 0 1 outputs low level outputs carrier pulse or high level no return zero data remote controller output control flag remc 0 1 outputs carrier pulse when nrz = 1 outputs high level when nrz = 1 nrz nrzb toe2 remc _ _ tc2 symbol remote controller output 6 70 1 32 4 5
chapter 5 peripheral hardware function 161 user s manual u10201ej2v4um00 (2) carrier generator operation the carrier generator operation is performed as follows. fig. 5-56 shows the configuration of the timer/event counter in the carrier generator mode. (a) operation of timer/event counter channel 1 timer/event counter channel 1 determines the reload interval between the no return zero buffer flag (nrzb) and no return zero flag (nrz). timer/event counter channel 1 operates as follows (for details, refer to 5.5.2 operation in 8-bit timer/event counter mode ). <1> a count pulse (cp) is selected by the mode register (tm1), and is input to the count register (t1). <2> the contents of t1 are compared with those of the modulo register (tmod1). when the contents of the two registers coincide, an interrupt request flag (irqt1) is set. at the time time, the timer out flip-flop (tout f/f) is inverted. (b) operation of timer/event counter channel 2 timer/event counter channel 2 generates a carrier clock and outputs the carrier according to the no return zero data. timer/event counter channel 2 operates as follows (for details, refer to 5.5.3 operation in pwm pulse generator mode (pwm mode) ). <1> a count pulse (cp) is selected by the mode register (tm2), and is input to the count register (t2). <2> the contents of t2 are compared with those of the high-level period setting modulo register (tmod2h). if the contents of the two registers coincide, a coincidence signal is generated, and the timer output flip-flop (tout f/f) is inverted. <3> the contents of t2 are compared with those of the modulo register (tmod2). when the contents of the two registers coincide, a coincidence signal is generated, and an interrupt request flag (irqt2) is set. at the same time, tout f/f is inverted. <4> the operations <2> and <3> are repeated. <5> the no return zero data is reloaded from nrzb to nrz when timer/event counter channel 1 generates an interrupt. <6> a carrier clock or high level is output when nrz is set to 1 by the remote controller output flag (remc). when nrz = 0, a low level is output. fig. 5-57 shows the timing of the carrier generator operation. the carrier generator operation is usually started by the following procedure:
chapter 5 peripheral hardware function 162 user s manual u10201ej2v4um00 <1> set the number of high levels of the carrier clock to tmod2h. <2> set the number of low levels of the carrier clock to tmod2. <3> set the output waveform to remc. <4> set the operation mode, count pulse, and start command to tm2. <5> set the number of counts to tmod1. <6> set the operation mode, count pulse, and start command to tm1. <7> set the no return zero data to be output next to nrzb before timer/event counter channel 1 generates an interrupt. caution set a value other than 00h to the modulo registers (tmod1, tmod2, and tmod2h). to use the timer/event counter output pin (pto1), set the p21 pin as follows: <1> clear the output latch of p21. <2> set port 2 in the output mode. <3> disconnect the pull-up resistor from port 2. <4> set the timer/event counter output enable flag (toe1) to 1. fig. 5-56 configuration in carrier generator mode mpx ti1 internal clock modulo register (tmod1) comparator count register (t1) cp tout f/f pto1 coincidence clear intt1 (lrqt1 set signal) mpx ti2 internal clock mpx comparator count register (t2) cp tout f/f clear intt2 (lrqt2 set signal) high-level period setting modulo register (tmod2h) modulo register (tmod2) coincidence nrzb nrz pto2 carrier clock reload
chapter 5 peripheral hardware function 163 user s manual u10201ej2v4um00 fig. 5-57 timing in carrier generator mode count pulse (cp) modulo register (tmod2) count register (t2) 12 i _ 1i 0 1 2 k _ 1k01234 k high-level period setting modulo register (tmod2h) i k0 carrier clock modulo register (tmod1) count register (t1) occurrence of interrupt (channel 1) no return zero flag (nrz) pto2 pin no return zero buffer flag (nrzb) n n0 1 2 n 0 1 2 n 0 1 2 n 0 1 2 n 0 1 irqt1 set irqt1 set irqt1 set irqt1 set irqt1 set 10 1 1 0 reload reload reload reload 01 1 0 1 0
chapter 5 peripheral hardware function 164 user s manual u10201ej2v4um00 remark if timer/event counter channel 1 generates an interrupt when the pto2 pin is high (when the no return zero flag (nrz) is 0 and carrier clock is high), the output of the pto2 pin will not correspond to the updated nrz contents until the carrier clock goes high next time. if timer/event counter channel 1 generates an interrupt when the pto2 pin is high (when nrz is 1 and carrier clock is high), the output of the pto2 pin will not correspond to the updated nrz contents until the carrier clock goes low. this processing functions to hold constant the high-level pulse width of the output carrier (refer to the figure below). carrier clock no return zero flag (nrz) pto2 pin pto2 does not go high even if nrz is set to "1" until the next carrier clock goes high. pto2 does not go low even if nrz is reset to "0" until the next carrier clock goes high.
chapter 5 peripheral hardware function 165 user s manual u10201ej2v4um00 (3) application of cg mode to use the timer/event counter as a carrier generator for remote controller signal transmission <1> to generate a carrier clock with a frequency of 38.0 khz (cycle of 26.3 s) and a duty factor of 1/3 set the higher 4 bits of the mode register (tm2) to 0011b and select 61.1 s (at 4.19 mhz) as the longest set time. set the lower 4 bits of tm2 to 1111b, and select the cg mode and count operation. then, issue the timer start command. set the timer output enable flag (toe2) to 1 to enable timer output. set the high-level period setting modulo register (tmod2h) as follows: 1 = 36.7 1 36 = 24h the set value of the modulo register (tmod2) is as follows: 1 = 73.4 1 72 = 48h
chapter 5 peripheral hardware function 166 user s manual u10201ej2v4um00 <2> to output a leader code with a 9-ms period to output a carrier clock and a 4.5-ms period to output a low level (refer to the figure below.) set the higher 4 bits of the mode register (tm1) to 0110b and select 15.6 ms (at 4.19 mhz) as the longest set time. set the lower 4 bits of tm1 to 1100b. then, select the 8-bit timer/event counter mode, count operation, and timer start command. the initial set value of the modulo register (tmod1) is as follows: 1 = 147.5 1 146 = 92h the set value for rewriting tmod1 is as follows: 1 = 73.7 1 73 = 49h set the higher 4 bits of tc2 to 0000b and disable gate control. set the lower 4 bits of tc2 to 0000b. the carrier clock is output when no return zero data is 1 , and the no return zero data to be output next is cleared to 0 .
chapter 5 peripheral hardware function 167 user s manual u10201ej2v4um00 <3> to output a custom code with a 0.56-ms period to output a carrier clock when data is 1 , a 1.69-ms to output a low level, a 0.56-ms to output a carrier clock when data is 0 , and a 0.56-ms period to output a low level (refer to the figure below.) set the higher 4 bits of the mode register (tm1) to 0011b and select 1.95 ms (at 4.19 mhz) as the longest set time. set the lower 4 bits of tm1 to 1100b. then, select the 8-bit timer/event counter mode, count operation, and timer start command. the initial set value of the modulo register (tmod1) is as follows: 1 = 73.3 1 = 72 = 48h during the period in which the carrier output of tmod1 is not performed, processing is executed for the duration of the same as the output period when data is 0 and for the duration three times that of the output period when data is 1 (software repeats three times the period in which carrier output is not performed when data is 0 ). set the higher 4 bits of tc2 to 0000b to disable gate control. set the lower 4 bits of tc2 to 0000b. the carrier clock is output when the no return zero data is 1 . the no return zero data to be output next is cleared to 0 . set the transmit data ( 0 or 1 ) to the bit sequential buffer. 0.56 ms 7.64 s 0.56 ms 0.56 ms 0.56 ms 1.69 ms data "1" data "0"
chapter 5 peripheral hardware function 168 user s manual u10201ej2v4um00
chapter 5 peripheral hardware function 169 user s manual u10201ej2v4um00 loop_c_0: sktclr irqt1 ; waits for low level output of preceding data (confirmation of end of preceding data) br loop_c_0 ; starts carrier output clr1 nrzb ; clears nrzb to 0 in advance so that first low level output is performed by irqt1 generated next call !get_data call !send_d_0 ske h, #1h ; if data gotten is 1, proceeds to second additional process- ing of low level output period (send_d_1) br send_1_f ; if data is 0, proceeds to transmission processing of next data with pto2 pin outputting low level call !send_d_1 br send_1_f send_end : ; completes transmission of 16 bits of data ;
chapter 5 peripheral hardware function 170 user s manual u10201ej2v4um00 5.5.6 notes on using timer/event counter (1) error when timer starts after the timer has been started (bit 3 of tmn has been set to 1 ), the time required for generation of the coincidence, which is calculated by the expression (contents of modulo register + 1) resolution, deviates by up to one clock of count pulse (cp). this is because count register tn is cleared asynchronously with cp, as shown below. if the frequency of cp is greater than one machine cycle, the time required for generation of the coincidence signal, which is calculated by the expression (modulo register contents + 1) resolution, deviates by up to cp2 clock after the timer has been started (bit 3 of tmn has been set to 1 ). this is because tn is cleared asynchronously with cp, based on the cpu clock, as shown below. 123 12 timer starts timer starts count pulse (cp) count register (tn) 0 0 11 2 timer starts timer starts count pulse (cp) count register (tn) 0 0
chapter 5 peripheral hardware function 171 user s manual u10201ej2v4um00 (2) note on starting timer usually, count register tn and interrupt request flag irqtn are cleared when the timer is started (bit 3 of tmn is set to 1 ). however, if the timer is in an operation mode, and if irqtn is set as soon as the timer is started, irqtn may not be cleared. this does not pose any problem when irqtn is used as a vector interrupt. in an application where irqtn is being tested, however, irqtn is not set after the timer has been started and this poses a problem. therefore, there is a possibility that the timer could be started as soon as irqtn is set to 1, either stop the timer once (by clearing the bit 2 of tmn to 0 ), or start the timer two times. example if there is a possibility that timer could be started as soon as irqtn is set sel mb15 mov xa, #0 mov tmn, xa ; stops timer mov xa, #4ch mov tmn, xa ; restarts or, sel mb15 set1 tmn.3 set1 tmn.3 ; restarts (3) error when count register is read the contents of the count register (tn) can be read at any time by using an 8-bit data memory manipulation instruction. while this instruction is executed, the count pulse (cp) is prevented from being changed. this means that tn is not changed. consequently, if tin input is used as the signal source of cp, cp is deleted by the instruction execution time. (this phenomenon does not occur if the internal clock is used as cp because it is synchronized with the instruction.) to input tin as cp and read the contents of tn, therefore, a signal with a pulse width that does not cause mis-count even if cp is deleted must be input. because counting is kept pending by a read instruction for the duration of 1 machine cycle, the pulse to be input to tin must be wider than 1 machine cycle. external clock (tln) instruction count pulse (cp) count register (tn) read instruction changes in count pulse are prevented by instruction count pulse is deleted by instruction. k _ 1 k k + 1 k + 2
chapter 5 peripheral hardware function 172 user s manual u10201ej2v4um00 (4) notes on changing count pulse when it is specified to change the count pulse (cp) by rewriting the contents of the timer/event counter mode register (tmn), the specification becomes valid immediately after execution of the instruction that commands the specification. a whisker-like cp (<1> or <2 > in the figure below) may be generated depending on the combination of the clocks for changing cp. in this case, a miscount may occur or the contents of the count register (tn) may be destroyed. to change cp, be sure to set the bit 3 of tmn bit to 1 and restart the timer at the same time. clock a specification clock b specification rewrite instruction rewrite instruction clock a specification clock a clock b count pulse (cp) clock a specification rewrite instruction rewrite instruction clock a specification clock a clock b count pulse (cp) <1> <2> clock b specification
chapter 5 peripheral hardware function 173 user s manual u10201ej2v4um00 (5) operation after changing modulo register the contents of the modulo register (tmodn) and high-level period setting modulo register (tmod2h) are changed as soon as an 8-bit data memory manipulation instruction has been executed. if the value of tmodn after change is less than the value of the count register (tn), tn continues counting. when an overflow occurs, tn starts counting again from 0. if the values of tmodn and tmod2h after the change are less than the values before change (n), it is necessary to restart the timer after changing tmodn and tmod2h. n rewrite instruction count pulse (cp) modulo register (tmodn) high-level period setting modulo register (tmod2h) m n count register (tn) coincidence signal coincidence signal 01 m 0 n count pulse (cp) modulo register (tmodn) high-level period setting modulo register (tmod2h) m x _ 1 count register (tn) n > x > m x01 255
chapter 5 peripheral hardware function 174 user s manual u10201ej2v4um00 (6) note on application of carrier generator (on starting) when the carrier clock is generated, after the timer has been started (by setting bit 3 of tm2 to 1 ), the high- level period of the initial carrier clock may deviate by up to one clock of count pulse (cp) (up to two clocks of cp if the frequency of cp is higher than one machine cycle) from the value calculated by the expression (contents of modulo register + 1) resolution (for details, refer to (1) error when timer starts ). to output a carrier as the initial code, if the timer is started (by setting bit 3 of tm2 to 1 ) after the no return zero flag (nrz) has been set to 1 , the high-level period of the initial carrier clock includes the possibility of an error that may occur when the timer is started. therefore, to output a carrier as the initial code, set nrz to 1 after the timer has been started (by setting bit 3 of tm2 to 1 ). 0 1 0 1 0 01 pto2 tout f/f nrz set1 nrz set1 tm2.3 error on start of timer is included 0 1 0 1 0 01 clock tout f/f nrz set1 nrz set1 tm2.3 error on start of timer is included pto2
chapter 5 peripheral hardware function 175 user s manual u10201ej2v4um00 (7) notes on application of carrier generator (reload) to output a carrier to the pto2 pin, the time required for the initial carrier to be generated deviates up to one clock of carrier clock after reloading (the contents of the no return zero buffer flag (nrzb) are transferred to the no return zero flag (nrz) by occurrence of the interrupt of timer/event counter channel 1, and the contents of nrz are updated to 1 ). this is because reloading is performed asynchronously with the carrier clock, as illustrated below in order to hold constant the high-level period of the carrier.
chapter 5 peripheral hardware function 176 user s manual u10201ej2v4um00 (8) notes on application of carrier generator (restarting) if forced reloading is performed by directly rewriting the contents of the no return zero flag (nrz) and then the timer is restarted (by setting bit 3 of tm2 to 1 ) when the carrier clock is high (tout f/f holds 1 ), the carrier may not be output to the pto2 pin as shown below. likewise, if forced reloading is performed by directly rewriting the contents of nrz and the timer is restarted (by setting bit 3 of tm2 to 1 ) when the carrier clock is high (tout f/f holds 1 ), the high-level period of the carrier output to the pto2 pin may be extended as shown below. 1 0 01 pto2 tout f/f nrz set1 nrz set1 tm2.3 carrier is not output 0 1 1 1 clock 00 1 0 01 pto2 tout f/f nrz clr1 nrz set1 tm2.3 high-level period of carrier is extended 0 1 1 1 clock 00
chapter 5 peripheral hardware function 177 user? manual u10201ej2v4um00 5.6 serial interface 5.6.1 function of serial interface the pd753036 has an 8-bit clocked serial interface that can operate in the following four modes: (1) operation stop mode this mode is used when serial transfer is not performed in order to reduce the power consumption. (2) 3-line serial i/o mode in this mode, three lines are used to transfer 8-bit data: serial clock (sck), serial output (so), and serial input (si). because transmission and reception can be simultaneously performed in this mode, the processing time of data transfer is very short. moreover, it can be specified whether serial data is transferred starting from the msb or lsb. this means that the pd753036 can communicate with any device. in the three-line serial i/o mode, the devices in the 75xl series, 75x series, and 78k series, and various peripheral i/o devices can be connected. (3) 2-line serial i/o mode in this mode, two lines, serial clock (sck) and serial data bus (sb0 or sb1), are used to transfer 8-bit data. by manipulating the output levels of these lines via software, the pd753036 can communicate with two or more devices. because the output levels of sck and sb0 (or sb1) can be manipulated via software, any transfer format can be used. therefore, a handshake line which has been conventionally necessary for connecting two or more devices is not necessary, and the i/o ports can be effectively used. (4) sbi mode (serial bus interface mode) in this mode, two lines, serial clock (sck) and serial data bus (sb0 or sb1), are used to communicate with two or more devices. this mode conforms to the nec serial bus format. in the sbi mode, the transmitter side can output an ?ddress?to select the device with which it is to communicate, ?ommand?to instruct the selected device of the operation to perform, and actual ?ata?onto the serial data bus. the receiver side can identify the received data as an ?ddress? ?ommand? or ?ata by hardware. this feature allows the sbi mode to use the i/o ports effectively in the same manner as the two-line serial i/o mode. in addition, the portion of the application program that controls the serial interface can be simplified.
chapter 5 peripheral hardware function 178 user? manual u10201ej2v4um00 fig. 5-58 example of sbi system configuration 5.6.2 configuration of serial interface fig. 5-59 shows the block diagram of the serial interface. master cpu sb0, sb1 sck slave cpu sb0, sb1 sck serial clock address command data address 1 #1 slave ic sb0, sb1 sck address n #n v dd
chapter 5 peripheral hardware function 179 user s manual u10201ej2v4um00 fig. 5-59 block diagram of serial interface internal bus 8 8 8/4 csim selector p03/si/sb1 selector p02/so/sb0 p01/sck p01 output latch 8 shift register (sio) address comparator slave address register (sva) (8) set clr d q (8) (8) bus release /command /acknowledge detection circuit serial clock counter serial clock control circuit sbic relt cmdt busy /acknowledge output circuit acke bsye ackt serial clock selector reld cmdd ackd intcsi control circuit intcsi (lrqcsi set signal) fx/2 3 fx/2 4 fx/2 6 tout f/f (from timer/event counter) external sck bit test bit manipulation bit test coincidence signal so latch
chapter 5 peripheral hardware function 180 user s manual u10201ej2v4um00 (1) serial operation mode register (csim) this 8-bit register specifies the operation mode and serial clock wake-up function of the serial interface (for details, refer to 5.6.3 (1) serial operation mode register (csim) ). (2) serial bus interface control register (sbic) this 8-bit register consists of bits that control the status of the serial bus and flags that indicate the various statuses of the data input from the serial bus. it is mainly used in the sbi mode (for details, refer to 5.6.3 (2) serial bus interface control register (sbic) ). (3) shift register (sio) this register converts 8-bit serial data into parallel data or 8-bit parallel data into serial data. it performs transmission or reception (shift operation) in synchronization with the serial clock. the user controls actual transmission or reception by writing data to the sio (for details, refer to 5.6.3 (3) shift register (sio) ). (4) so latch this latch holds the levels of the so/sb0 and si/sb1 pins. it can also be controlled directly via software. in the sbi mode, this latch is set when sck has been asserted eight times (for details, refer to 5.6.3 (2) serial bus interface control register (sbic) ). (5) serial clock selector this selects the serial clock to be used. (6) serial clock counter this counter counts the number of serial clocks output or input when transmission or reception operation is performed in order to check whether 8-bit data has been transmitted or received. (7) slave address register (sva) and address comparator in sbi mode these register and comparator are used when the pd753036 is used as a slave device. the slave sets its specification number (slave address value) to the sva. the master outputs a slave address to select a specific slave. the address comparator of the slave compares the slave address the slave has received from the master with the value of the sva. when the address coincides with the sva value, the slave is selected. in 2-line serial i/o mode and sbi mode when the pd753036 is used as a slave or master, these register and comparator detect an error (for details, refer to 5.6.3 (4) slave address register (sva) ).
chapter 5 peripheral hardware function 181 user s manual u10201ej2v4um00 (8) intcsi control circuit this circuit controls generation of an interrupt request. the interrupt request (intcsi) is generated in the following cases. when the interrupt request is generated, an interrupt request flag (irqcsi) is set (refer to fig. 6-1 block diagram of interrupt control circuit ). in 3-line and 2-line serial i/o modes the interrupt request is generated each time eight serial clocks have been counted. in sbi mode when wup note = 0 ... the interrupt request is generated each time eight serial clocks have been counted. when wup = 1 ... the interrupt request is generated when the value of sva and that of sio coincide after an address has been received. note wup ... wake-up function specification bit (bit 5 of csim) (9) serial clock control circuit this circuit controls the supply of the serial clock to the shift register. it also controls the clock output to the sck pin when the internal system clock is used. (10) busy/acknowledge output circuit and bus release/command/acknowledge circuit these circuits output and detect control signals in the sbi mode. they do not operate in the three-line and two-line serial i/o modes. (11) p01 output latch this latch generates the serial clock via software after eight serial clock have been generated. it is set to 1 when the reset signal is input. to select the internal system clock as the serial clock, set the p01 output latch to 1 .
chapter 5 peripheral hardware function 182 user s manual u10201ej2v4um00 5.6.3 register functions (1) serial operation mode register (csim) fig. 5-60 shows the format of the serial operation mode register (csim). csim is an 8-bit register that specifies the operation of the serial interface, serial clock, and wake-up function. this register is manipulated by an 8-bit memory manipulation instruction. the higher 3 bits of this register can also be manipulated in 1-bit units. to manipulate a bit, use the name of the bit. some bits of this register can only be read, and some can only be written (refer to fig. 5-60 ). bit 6 can only be tested. data written to this bit is invalid. all the bits are cleared to 0 when the reset signal is asserted. fig. 5-60 format of serial operation mode register (csim) (1/4) remarks 1. (r) : read only 2. (w) : write only 765432 10 csim0 csim1 csim3 csim2 csim4 wup coi csie address csim fe0h symbol serial clock select bits (w) serial interface operation mode select bits (w) wake-up function specification bit (w) signal from address comparator (r) serial interface operation enable/disable bit (w)
chapter 5 peripheral hardware function 183 user s manual u10201ej2v4um00 fig. 5-60 format of serial operation mode register (csim) (2/4) serial interface operation enable/disable bit (w) operation of shift register serial clock counter irqcsi flag so/sb0 and si/sb1 pins csie 0 shift operation disabled clear retained port 0 function 1 shift operation enabled count operation can be set function in each mode and port 0 function shared signal from address comparator (r) coi note clear condition (coi = 0) set condition (coi = 1) when data of slave address register (sva) and when data of slave address register (sva) and data of shift register do not coincide data of shift register coincide note coi can be read before the start of serial transfer and after completion of the serial transfer. an undefined value is read if this bit is read during transfer. any data written to coi by an 8-bit manipulation instruction is ignored. wake-up function specification bit (w) wup 0 sets irqcsi each time serial transfer is completed in each mode 1 used in sbi mode only. sets irqcsi only when an address received after the bus has been released coincides with the data of the slave address register (wake-up status). sb0/sb1 goes into a high-impedance state. caution if wup is set to 1 while the busy signal is output, the busy status is not released. the sbi outputs the busy signal until the serial clock (sck) falls the next time after the busy release command has been issued. before setting wup to 1, be sure to release the busy status and make sure that the sb0 (or sb1) pin has gone high.
chapter 5 peripheral hardware function 184 user s manual u10201ej2v4um00 fig. 5-60 format of serial operation mode register (csim) (3/4) serial interface operation mode select bit (w) csim4 csim3 csim2 operation mode bit order of shift register so pin function si pin function 0 0 3-line serial sio 7-0 ? xa so/p02 si/p03 (input) i/o mode (msb first) (cmos output) 1 sio 0-7 ? xa (lsb first) 0 1 0 sbi mode sio 7-0 ? xa sbk0/p02 p03 input (msb first) (n-ch open-drain i/o) 1 p02 input sb1/p03 (n-ch open-drain i/o) 0 1 1 2-line serial i/o sio 7-0 ? xa sb0/p02 p03 input mode (msb first) (n-ch open-drain i/o) 1 p02 input sb1/p03 (n-ch open-drain i/o) remark : don t care serial clock select bit (w) serial clock sck csim1 csim0 pin 3-line serial i/o mode sbi mode 2-line serial i/o mode mode 0 0 external clock input to sck pin input 0 1 timer/event counter output (to) output 10f x /2 4 (375 khz at 6.0 mhz, 262 khz at 4.19 mhz) f x /2 6 (93.8 khz at 6.0 mhz, 11f x /2 3 (750 khz at 6.0 mhz, 524 khz at 4.19 mhz) 65.5 khz at 4.19 mhz)
chapter 5 peripheral hardware function 185 user s manual u10201ej2v4um00 fig. 5-60 format of serial operation mode register (csim) (4/4) remarks 1. each mode can be selected by setting csie, csim3, and csim2. csie csim3 csim2 operation mode 0 operation stop mode 10 3-line serial i/o mode 1 1 0 sbi mode 1 1 1 2-line serial i/o mode 2. p01/sck pin is set in the following status by the setting of csie, csim1, and csim0: csie csim1 csim0 status of p01/sck pin 0 0 0 input port 1 0 0 high-impedance 0 0 1 high-level output 010 011 1 0 1 serial clock output 1 1 0 (high-level output) 111 3. clear csie during serial transfer in the following procedure: <1> clear the interrupt enable flag to disable the interrupt. <2> clear csie. <3> clear the interrupt request flag. examples 1. to select f x /2 4 as the serial clock, generate serial interrupt irqcsi each time serial transfer is completed. then, select a mode in which serial transfer is performed in sbi mode with the sb0 pin as the serial data bus sel mb15 ; or clr1 mbe mov xa, #10001010b mov csim, xa ; csim 10001010b 2. to enable serial transfer according to the contents of csim sel mb15 ; or clr1 mbe set1 csie
chapter 5 peripheral hardware function 186 user s manual u10201ej2v4um00 (2) serial bus interface control register (sbic) fig. 5-61 shows the format of the serial bus interface control register (sbic). sbic is an 8-bit register that consists of bits that control the serial bus and flags that indicate the status of the data input from the serial bus. this register is manipulated by a bit manipulation instruction. it cannot be manipulated by a 4- or 8-bit memory manipulation instruction. some bits of this register can only be read, and some can only be written (refer to fig. 5-61 ). all the bits are cleared to 0 when the reset signal is asserted. caution only the following bits can be used in the three-line and two-line serial i/o modes: bus release trigger bit (relt) . sets so latch command trigger bit (cmdt) ... clears so latch fig. 5-61 format of serial bus interface control register (sbic) (1/3) remarks 1. (r) : read only 2. (w) : write only 3. (r/w) : read/write 765432 10 relt cmdt cmdd reld ackt acke ackd bsye address sbic fe2h symbol bus release trigger bit (w) command trigger bit (w) bus release detection flag (r) command detection flag (r) acknowledge trigger bit (w) acknowledge enable bit (r/w) acknowledge detection flag (r) busy enable bit (r/w)
chapter 5 peripheral hardware function 187 user s manual u10201ej2v4um00 fig. 5-61 format of serial bus interface control register (sbic) (2/3) busy enable bit (r/w) bsye 0 <1> disables automatic output of busy signal <2> stops output of busy signal in synchronization with falling edge of sck immediately after clear instruction has been executed 1 outputs busy signal in synchronization with falling of sck, after outputting acknowledge signal acknowledge detection flag (r) ackd clear condition (ackd = 0) set condition (ackd = 1) <1> at start of transfer when acknowledge signal (ack) is detected <2> when reset signal is asserted (synchronized with falling edge of sck) acknowledge enable bit (r/w) acke 0 disables automatic output of acknowledge signal (ack) (output by ackt is enabled) 1 when set before end of transfer ack is output in synchronization with 9th sck when set after end of transfer ack is output in synchronization with sck immediately after execution of set instruction acknowledge trigger bit (w) ackt if this bit is set after end of transfer, ack is output in synchronization with next sck. this bit is automatically cleared to 0 after ack signal has been output. cautions 1. do not set this bit to 1 before the end of serial transfer and during transfer. 2. ackt cannot be cleared by software. 3. to set ackt, clear acke to 0. command detection flag (r) cmdd clear condition (cmdd = 0) set condition (cmdd = 1) <1> when transfer start instruction is executed when command signal (cmd) is detected <2> when bus release signal (rel) is detected) <3> when reset signal is asserted <4> csie = 0 (refer to fig. 5-60 .) bus release detection flag (r) reld clear condition (reld = 0) set condition (reld = 1) <1> when transfer start instruction is executed when bus release signal (rel) is detected <2> when reset signal is asserted <3> csie = 0 (refer to fig. 5-60 .) <4> when sva and sio do not coincide when address is received
chapter 5 peripheral hardware function 188 user s manual u10201ej2v4um00 fig. 5-61 format of serial bus interface control register (sbic) (3/3) command trigger bit (w) cmdt this bit controls output trigger of command signal (cmd). when this bit is set to 1, so latch is cleared to 0. subsequently, the cmdt bit is automatically cleared to 0. caution do not set sb0 (or sb1) during serial transfer. be sure to set it before the start of or after the end of transfer. bus release trigger bit (w) relt this bit controls output trigger of bus release signal (rel). when this bit is set to 1, so latch is set to 1. subsequently, the relt bit is automatically cleared to 0. caution do not set sb0 (or sb1) during serial transfer. be sure to set it before the start of or after the end of transfer. examples 1. to output a command signal sel mb15 ; or clr1 mbe set1 cmdt 2. to test reld and cmdd to identify the types of received data and perform different processing. wup = 1 in the interrupt routine so that processing is performed only when address coincidence occurs. sel mb15 skf reld ; tests reld br !adrs skt cmdd ; tests cmdd br !data br !cmd cmd; ; ................................. interprets command data ; ................................. ; processes data adrs ; ................................. ; decodes address
chapter 5 peripheral hardware function 189 user s manual u10201ej2v4um00 (3) shift register (sio) fig. 5-62 shows the configuration of the peripheral circuits of the shift register (sio). sio is an 8-bit register that converts parallel data to serial data or vice versa and performs serial transmission or reception (shift operation) in synchronization with the serial clock. serial transfer is started by writing data to sio. the data written to sio is output to the serial output (so) or serial data bus (sb0 or sb1) line during transmission. data is read from the serial input (si) or sb0 or sb1 to sio during reception. sio can be read or written by an 8-bit manipulation instruction. when the reset signal is asserted during operation of sio, the value of sio becomes undefined. when the reset signal is asserted in the standby mode, the value of sio is retained. the shift operation is stopped after 8-bit data has been transmitted or received. fig. 5-62 peripheral circuits of shift register sio can be read or serial transfer (write) can be started with the following timing: when the serial interface operation enable/disable bit (csie) = 1, except when csie is set to 1 after data has been written to the shift register when the serial clock is masked after 8-bit serial data has been transferred when sck is high be sure to write or read data to or from the sio when sck is high. the input pin of the data bus is shared with the output pin in the two-line serial i/o mode and sbi mode. the output pin is of n-ch open-drain configuration. therefore, set ffh to the sio of the device that is to receive data. internal bus address comparator dq set clr clk relt cmdt so iatch busy/ack shift register csim shift clock n-ch open-drain output
chapter 5 peripheral hardware function 190 user s manual u10201ej2v4um00 (4) slave address register (sva) sva is an 8-bit register that sets a slave address (specification number). this register can be manipulated by an 8-bit manipulation instruction. the value of sva is undefined when the reset signal is asserted. however, it is retained if the reset signal is asserted in the standby mode. (a) detection of slave address (in sbi mode) when the pd753036 is connected to the serial bus as a slave device, the sva is used to set the slave address (specification number) of the pd753036. the master outputs a slave address to the slaves connected to the bus, to select a specific slave. the slave address output from the master is compared with the value of the sva of the slave by the address comparator of the slave. when the two addresses coincide, the slave is selected. at this time, the bit 6 (coi) of the serial operation mode register (csim) is set to 1 . when an address is received from the master, and when coincidence between the received address and the address set to the sva is not detected, the bus release detection flag (reld) is cleared to 0. irqcsi is set only if coincidence is detected when wup = 1. this interrupt function allows the slave ( pd753036) to learn that the master has issued a request for communication. (b) detection of error (in 2-line serial i/o mode and sbi mode) the sva detects an error in the following cases: when the pd753036 operates as the master and transmits addresses, commands, and data when the pd753036 transmits data as a slave device for details, refer to 5.6.6 (6) or 5.6.7 (8) error detection .
chapter 5 peripheral hardware function 191 user s manual u10201ej2v4um00 5.6.4 operation stop mode the operation stop mode is used when serial transfer is not performed, to reduce the power consumption. in this mode, the shift register does not perform its shift operation. therefore, it can be used as an ordinary 8- bit register. when the reset signal is input, the operation stop mode is set. the p02/so/sb0 and p03/si/sb1 pins are set in the input port mode. the p01/sck pin can be used as an input port pin if so specified by the serial operation mode register. [register setting] the operation stop mode is set by using the serial operation mode register (csim) (for the format of the csim, refer to 5.6.3 (1) serial operation mode register (csim) ). the csim is manipulated in 8-bit units. however, the csie bit of this register can be manipulated in 1-bit units. the name of the bit can be used for manipulation. csim is initialized to 00h at reset. the shaded portions in the figure below indicate the bits used in the operation stop mode. note this bit can select the status of the p01/sck pin. remark (r) : read only (w) : write only serial interface operation enable/disable bit (w) operation of shift so/sb0 and si/sb1 serial clock counter irqcsi flag register pins csie 0 shift operation disabled cleared retained dedicated to port 0 function 765432 10 address symbol serial clock select bits (w) note serial interface operation mode select bits (w) wake-up function specification bit (w) coincidence signal from address comparator (r) serial interface operation enable/disable bit (w) csim0 csim1 csim3 csim2 csim4 wup coi csie csim fe0h
chapter 5 peripheral hardware function 192 user s manual u10201ej2v4um00 serial clock select bit (w) the p01/sck pin is set in the following status according to the setting of the csim0 and csim1 bits. csim1 csim0 status of p01/sck pin 0 0 high impedance 0 1 high level 10 11 clear the csie bit in the following procedure during serial transfer: <1> clear the interrupt enable flag (iecsi) to disable the interrupt. <2> clear csie. <3> clear the interrupt request flag (irqcsi).
chapter 5 peripheral hardware function 193 user s manual u10201ej2v4um00 5.6.5 operation in 3-line serial i/o mode in the three-line operation mode, the pd753036 can be connected to microcontrollers in the 75xl series, 75x series, and 78k series, and various peripheral i/o devices. in this mode, communication is established by using three lines: serial clock (sck), serial output (so), and serial input (si). fig. 5-63 example of system configuration in 3-line serial i/o mode 3-line serial i/o ? 3-line serial i/o remark the pd753036 can be also used as a slave cpu. (1) register setting when the three-line serial i/o mode is used, the following two registers must be set: serial operation mode register (csim) serial bus interface control register (sbic) sck master cpu pd753036 sck so si si so slave cpu
chapter 5 peripheral hardware function 194 user s manual u10201ej2v4um00 (a) serial operation mode register (csim) when the three-line serial i/o mode is used, set the csim as shown below (for the format of the csim, refer to 5.6.3 (1) serial operation mode register (csim) ). the csim is manipulated by using an 8-bit manipulation instruction. bits 7, 6, and 5 can also be manipulated in 1-bit units. the contents of the csim are cleared to 00h at reset. the shaded portion in the figure indicates the bits used in the three-line serial i/o mode. remark (r) : read only (w) : write only serial interface operation enable/disable bit (w) operation of shift so/sb0 and si/sb1 serial clock counter irqcsi flag register pins csie 1 shift operation enabled count operation can be set function in each mode and port 0 function shared signal from address comparator (r) coi note clear condition (coi = 0) set condition (coi = 1) when data of slave address register (sva) and when data of slave address register (sva) and data of shift register do not coincide data of shift register coincide note coi can be read before the start of serial transfer and after completion of the serial transfer. an undefined value is read if this bit is read during transfer. the data written to coi by an 8-bit manipulation instruction is ignored. wake-up function specification bit (w) wup 0 sets irqcsi each time serial transfer is completed 765432 10 address symbol serial clock select bits (w) serial interface operation mode select bits (w) wake-up function specification bit (w) coincidence signal from address comparator (r) serial interface operation enable/disable bit (w) csim0 csim1 csim3 csim2 csim4 wup coi csie csim fe0h
chapter 5 peripheral hardware function 195 user s manual u10201ej2v4um00 serial interface operation mode select bit (w) csim4 csim3 csim2 bit order of shift register so pin function si pin function 0 0 sio 7-0 ? xa so/p02 si/p03 (msb first) (cmos output) (input) 1 sio 0-7 ? xa (lsb first) remark : don t care serial clock select bit (w) csim1 csim0 serial clock sck pin mode 0 0 external clock input to sck pin input 0 1 timer/event counter output (to) output 10f x /2 4 (262 khz) note 11f x /2 4 (262 khz) note note ( ): f x = 4.19 mhz (b) serial bus interface control register (sbic) when the three-line serial i/o mode is used, set sbic as shown below (for the format of sbic, refer to 5.6.3 (2) serial bus interface control register (sbic) ). this register is manipulated by using a bit manipulation instruction. the contents of sbic are cleared to 00h at reset. the shaded portion in the figure indicate the bits used in the three-line serial i/o mode. remark (w) : write only command trigger bit (w) cmdt this bit controls the output trigger of a command signal (cmd). when this bit is set to 1, the so latch is cleared to 0. subsequently, the cmdt bit is automatically cleared to 0. bus release trigger bit (w) relt this bit controls the output trigger of a bus release signal (rel). when this bit is set to 1, the so latch is set to 1. subsequently, the relt bit is automatically cleared to 0. caution do not use the bits of the sbic register other than cmdt and relt in the three-line serial i/o mode. bus release trigger bit (w) command trigger bit (w) 765432 10 relt cmdt cmdd reld ackt acke ackd bsye address sbic fe2h symbol do not use these bits in 3-line serial l/o mode.
chapter 5 peripheral hardware function 196 user s manual u10201ej2v4um00 (2) communication operation in the three-line serial i/o mode, data is transmitted or received in 8-bit units. each bit of the data is transmitted or received in synchronization with the serial clock. the shift register performs its shift operation in synchronization with the falling edge of the serial clock (sck). the transmit data is retained by the so latch and output from the so pin. the receive data input to the si pin is latched to the shift register at the rising edge of sck. when 8-bit data has been completely transferred, the shift register automatically stops, and an interrupt request flag (irqcsi) is set. fig. 5-64 timing in 3-line serial i/o mode si sck 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so do7 do6 do5 do4 do3 do2 do1 do0 irqcsi transfer starts is synchronization with falling edge of sck end of transfer execution of instruction that writes data to sio (transfer start command)
chapter 5 peripheral hardware function 197 user s manual u10201ej2v4um00 timing at which shift register can be read/ written and serial transfer can be started because the so pin is a cmos output pin and outputs the status of the so latch, the output status of the so pin can be manipulated by setting the relt and cmdt bits. however, do not perform this manipulation during serial transfer. the output status of the sck pin can be controlled by manipulating the p01 latch in the output mode (mode of the internal system clock)(refer to 5.6.8 manipulating sck pin output ). (3) selecting serial clock the serial clock is selected by using the bits 0 and 1 of the serial operation mode register (csim). the following four types of serial clocks can be selected: table 5-9 selecting serial clock and application (in 3-line serial i/o mode) mode register serial clock csim csim source masking serial application 1 0 clock 0 0 external automatically <1> in operation stop mode (csie = 0) slave cpu sck masked at end <2> if serial clock is masked after 8-bit 0 1 tout of transfer of serial transfer half duplex start-stop f/f 8-bit data <3> when sck is high synchronization transfer (software control) 10f x /2 4 medium-speed serial transfer 11f x /2 3 high-speed serial transfer (4) signals fig. 5-65 illustrates the operations of relt and cmdt. fig. 5-65 operations of relt and cmdt relt cmdt so latch
chapter 5 peripheral hardware function 198 user s manual u10201ej2v4um00 (5) selecting msb or lsb in the three-line serial i/o mode, a function is provided to enable the user to select whether serial data is transferred starting from the msb or lsb. fig. 5-66 shows the configuration of the shift register and internal bus. as shown in this figure, the msb or lsb can be inverted to read or write data. whether transfer is started from the msb or lsb can be specified by using the bit 2 of the serial operation mode register (csim). fig. 5-66 transfer bit select circuit the bit (msb or lsb) from which data transfer is started is selected by changing the bit sequence in which the data is written to the shift register (sio). the shift sequence of sio is always the same. therefore, select the bit from which data transfer is started before writing data to the shift register. 7 6 internal bus 1 0 lsb first msb first read/write gate si shift register (sio) read/write gate so sck dq so latch
chapter 5 peripheral hardware function 199 user s manual u10201ej2v4um00 (6) starting transfer serial transfer is started when the transfer data is set to the shift register (sio), if the following two conditions are satisfied: serial interface operation enable/disable bit (csie) = 1 if the internal serial clock is stopped after 8-bit serial transfer or if sck is high caution transfer is not started even if csie is set to 1 after the data has been written to the shift register. when 8-bit transfer has been completed, the serial transfer is automatically stopped, and an interrupt request flag (irqcsi) is set. example to transfer the data of an ram specified by the hl register to sio and, at the same time, load the data of sio to the accumulator and start serial transfer mov xa, @hl ; takes out transfer data from ram sel mb15 ; or clr1 mbe xch xa, sio ; exchanges transmit data and receive data, and starts transfer (7) application of 3-line serial i/o mode examples 1. to transfer data with msb first with 262-khz transfer clock (at 4.19 mhz) (master operation)
chapter 5 peripheral hardware function 200 user s manual u10201ej2v4um00 examples 2. to transfer data with lsb first with an external clock (slave operation) (in this example, a function to invert msb and lsb is used to read/write the shift register.)
chapter 5 peripheral hardware function 201 user s manual u10201ej2v4um00 examples 3. to transmit or receive data at high speeds using a 524-khz (at 4.19 mhz) transfer clock
chapter 5 peripheral hardware function 202 user s manual u10201ej2v4um00 5.6.6 operation in 2-line serial i/o mode the two-line serial i/o mode can be used in any communication format if so specified by the program. basically, communication is established by using two lines: serial clock (sck) and serial data input/output (sb0 or sb1). fig. 5-67 example of system configuration in 2-line serial i/o mode 2-line serial i/o ? 2-line serial i/o remark the pd753036 can be also used as a slave cpu. (1) register setting when the two-line serial i/o mode is used, the following two registers must be set: serial operation mode register (csim) serial bus interface control register (sbic) sck pd753036 sb0, sb1 slave cpu sck sb0, sb1 master cpu v dd
chapter 5 peripheral hardware function 203 user s manual u10201ej2v4um00 (a) serial operation mode register (csim) when the two-line serial i/o mode is used, set the csim as shown below (for the format of the csim, refer to 5.6.3 (1) serial operation mode register (csim) ). the csim is manipulated by using an 8-bit manipulation instruction. bits 7, 6, and 5 can also be manipulated in 1-bit units. the contents of the csim are cleared to 00h at reset. the shaded portion in the figure indicates the bits used in the two-line serial i/o mode. remark (r) : read only (w) : write only serial interface operation enable/disable bit (w) operation of shift so/sb0 and si/sb1 serial clock counter irqcsi flag register pins csie 1 shift operation enabled count operation can be set function in each mode and port 0 function shared signal from address comparator (r) coi note clear condition (coi = 0) set condition (coi = 1) when data of slave address register (sva) and when data of slave address register (sva) and data of shift register do not coincide data of shift register coincide note coi can be read before the start of serial transfer and after completion of the serial transfer. an undefined value is read if this bit is read during transfer. the data written to coi by an 8-bit manipulation instruction is ignored. wake-up function specification bit (w) wup 0 sets irqcsi each time serial transfer is completed 765432 10 address symbol serial clock select bits (w) serial interface operation mode select bits (w) wake-up function specification bit (w) coincidence signal from address comparator (r) serial interface operation enable/disable bit (w) csim0 csim1 csim3 csim2 csim4 wup coi csie csim fe0h
chapter 5 peripheral hardware function 204 user s manual u10201ej2v4um00 serial interface operation mode select bit (w) csim4 csim3 csim2 bit order of shift register so pin function si pin function 011sio 7-0 ? xa sb0/p02 p03 input (msb first) (n-ch open-drain i/o) 1 p02 input sb1/p03 (n-ch open-drain i/o) serial clock select bit (w) csim1 csim0 serial clock sck pin mode 0 0 external clock input to sck pin input 0 1 timer/event counter output (to) output 10f x /2 6 (65.5 khz) note 11 note ( ) : f x = 4.19 mhz (b) serial bus interface control register (sbic) when the two-line serial i/o mode is used, set sbic as shown below (for the format of sbic, refer to 5.6.3 (2) serial bus interface control register (sbic) ). this register is manipulated by using a bit manipulation instruction. the contents of sbic are cleared to 00h at reset. the shaded portion in the figure indicate the bits used in the two-line serial i/o mode. remark (w) : write only command trigger bit (w) cmdt this bit controls the output trigger of a command signal (cmd). when this bit is set to 1, the so latch is cleared to 0. after that, the cmdt bit is automatically cleared to 0. bus release trigger bit (w) relt this bit controls the output trigger of a bus release signal (rel). when this bit is set to 1, the so latch is set to 1. after that, the relt bit is automatically cleared to 0. caution do not use the bits of the sbic register other than cmdt and relt in the two-line serial i/o mode. bus release trigger bit (w) command trigger bit (w) 765432 10 relt cmdt cmdd reld ackt acke ackd bsye address sbic fe2h symbol do not use these bits in 2-line serial l/o mode.
chapter 5 peripheral hardware function 205 user s manual u10201ej2v4um00 (2) communication operation in the two-line serial i/o mode, data are transmitted or received in 8-bit units. data are transmitted or received in synchronization with the serial clock, on a bit-by-bit basis. the shift register performs its shift operation in synchronization with the falling edge of the serial clock (sck). the transmit data is retained by the so latch and output from the sb0/p02 (or sb1/p03) pin with the msb first. the receive data input from the sb0 pin (or sb1) is latched to the shift register at the rising edge of sck. when the 8-bit data has been completely transferred, the shift register is automatically stopped, and an interrupt request flag (irqcsi) is set. fig. 5-68 timing in 2-line serial i/o mode the sb0 (or sb1) pin specified as the serial data bus is an n-ch open-drain i/o pin, and must be externally pulled up. because it is necessary to turn off the n-ch transistor when data is received, write ffh to sio in advance. because the sb0 (or sb1) pin outputs the status of the so latch, the output status of the sb0 (or sb1) pin can be manipulated by setting the relt and cmdt bits. however, do not perform this manipulation during serial transfer. the output status of the sck pin can be controlled by manipulating the p01 output latch in the output mode (mode of the internal system clock) (refer to 5.6.8 manipulating sck pin output ). 123 4 5 6 7 8 sck d7 d6 d5 d4 d3 d2 d1 d0 sb0, sb1 irqcsi transfer started in synchronization with falling of sck end of transfer executes instruction to write data to sio (transfer start command)
chapter 5 peripheral hardware function 206 user s manual u10201ej2v4um00 timing at which shift register can be read/ written and serial transfer can be started (3) selecting serial clock the serial clock is selected by using the bits 0 and 1 of the serial operation mode register (csim). the following three types of serial clocks can be selected: table 5-10 selecting serial clock and application (in 2-line serial i/o mode) mode register serial clock csim csim source masking serial application 1 0 clock 0 0 external automatically <1> in operation stop mode (csie = 0) slave cpu sck masked at end <2> if serial clock is masked after 8-bit 0 1 tout of transfer of serial transfer serial transfer at any f/f 8-bit data <3> when sck is high speed 10f x /2 6 low-speed serial 11 transfer (4) signals fig. 5-69 illustrates the operations of relt and cmdt. fig. 5-69 operations of relt and cmdt relt cmdt so latch
chapter 5 peripheral hardware function 207 user s manual u10201ej2v4um00 (5) starting transfer serial transfer is started when the transfer data is set to the shift register (sio), if the following two conditions are satisfied: serial interface operation enable/disable bit (csie) = 1 if the internal serial clock is stopped after 8-bit serial transfer or if sck is high cautions 1. transfer is not started even if csie is set to 1 after the data has been written to the shift register. 2. because it is necessary to turn off the n-ch transistor when data is received, write ffh to sio in advance. when 8-bit transfer has been completed, the serial transfer is automatically stopped, and an interrupt request flag (irqcsi) is set. (6) error detection in the two-line serial i/o mode, because the status of the serial bus sb0 or sb1 during transmission is also loaded to the shift register sio of the device transmitting data, an error can be detected by the following methods: (a) by comparing sio data before and after transmission if the two data differ from each other, it may be assumed that a transmission error has occurred. (b) by using slave address register (sva) the transmit data is set to sio and sva and transmission is executed. after transmission, the coi bit (coincidence signal from the address comparator) of the serial operation mode register (csim) is tested. if this bit is 1 , the transmission has been completed normally. if it is 0 , it may be assumed that a transmission error has occurred.
chapter 5 peripheral hardware function 208 user s manual u10201ej2v4um00 (7) application of two-line serial i/o mode the two-line serial i/o mode can be used to connect plural devices by configuring a serial bus. example to configure a system by connecting the pd753036 as the master and pd75104, pd75402a, and pd7225g as slaves the si and so pins of the pd75104 are connected together. when serial data is not output, the serial operation mode register is manipulated and the output buffer is turned off to release the bus. because the so pin of the pd75402a cannot go into a high-impedance state, a transistor is connected to the so pin as shown in the figure, so that the so pin can be used as an open-collector output pin. when data is input to the pd75402a, the transistor is turned off by writing 00h to the shift register in advance. when each microcontroller outputs data is determined in advance. the serial clock is output by the pd753036, which is the master. all the slave microcontrollers operate on an external clock. pd753036 (master) port sck pd7225g cs sck si so/sb0 pd75402a so pd75104 sck si so sck si v dd
chapter 5 peripheral hardware function 209 user? manual u10201ej2v4um00 5.6.7 operation in sbi mode sbi (serial bus interface) is a high-speed serial interface method conforming to nec? serial bus format. sbi is a high-speed serial bus with a single master and is based on a clocked serial i/o method added with functions to configure a bus, so that communication can be established among two or more devices with two signal lines. therefore, the number of ports and the wiring length of the printed circuit board can be reduced when a serial bus is configured among two or more microcontrollers and peripheral ics. the master can output an ?ddress?to select a slave device with which it is to communicate, a ?ommand?to instruct the slave of the operation to be performed, and actual ?ata?to the slave via the serial data bus. the slave identifies the data it has received from the master as an ?ddress? ?ommand? or ?ata?by using hardware. this sbi function simplifies the portion of the application program that controls the serial interface. the sbi function is provided in many devices such as the ?5xl series? ?5x series? and 8- and 16-bit single- chip microcontrollers in the ?8k series? fig. 5-70 shows an example of the configuration of the serial bus when cpus and peripheral ics have a serial interface conforming to sbi.
chapter 5 peripheral hardware function 210 user? manual u10201ej2v4um00 fig. 5-70 example of sbi system configuration cautions 1. because the serial data bus pin sb0 (or sb1) serves as an open-drain output pin in the sbi mode, the serial data bus line is wired-ored. the serial data bus line must be connected with a pull-up resistor. 2. when the master is exchanged with a slave, the mode of the serial clock line (sck) is changed between input and output asynchronously between the master and slave. therefore, a pull- up resistor must be connect to the sck line. pd753036 sck sb0 (sb1) pd753036 sb0 (sb1) sck sb0 (sb1) sck v dd address n address 2 address 1 . . . . . . slave ic slave cpu sb0 (sb1) sck master cpu slave cpu
chapter 5 peripheral hardware function 211 user s manual u10201ej2v4um00 (1) function of sbi if two or more devices are connected to configure a serial bus with the existing serial i/o method, many ports and wiring are necessary for distinguishing among the chip select signal, command, and data, and for identifying the busy status, because the existing serial i/o method only provides a data transfer function. moreover, if software is used to distinguish the signals and identify the status, the workload of the software increases. in the sbi mode, the serial bus can be configured by using only two lines: serial clock sck and serial data bus sb0 or sb1. therefore, the number of ports can be reduced and the wiring on the printed circuit board can be shortened. the functions of the sbi mode are described below. (a) address/command/data identification function serial data is identified as an address, command, or data. (b) chip select function by using address the master transmits an address to a slave to select the slave (chip select). (c) wake-up function the slave can judge whether it has received an address (whether the slave has received the chip select signal from the master) by using the wake-up function (which can be set or cleared via software). when the wake-up function is set, an interrupt (irqcsi) is generated when the slave has received an address coinciding with its own address. therefore, even when the master communicates with two or more slaves, the slaves other than that selected by the master can operate independently of the serial communication between the master and selected slave. (d) acknowledge signal (ack) control function the acknowledge signal is controlled so that confirmation can be made that serial data has been received. (e) busy signal (busy) control function the busy signal that notifies the master of the busy status of a slave is controlled. (2) definition of sbi this paragraph describes the format of the serial data in the sbi mode and the meanings of the signals used. the serial data transferred in the sbi mode are classified into address , command , and data . fig. 5-71 shows the transfer timing of the address, command, and data.
chapter 5 peripheral hardware function 212 user s manual u10201ej2v4um00 fig. 5-71 sbi transfer timing sck sb0, sb1 sck sb0, sb1 sck sb0, sb1 89 9 a7 a0 ack busy c7 c0 ack busy ready 89 d7 d0 ack busy ready address transfer command transfer data transfer bus release signal command signal the bus release and command signals are output by the master. busy is output by the slave. ack can be output by both the master and slave (usually, this signal is output by the receiver of 8-bit data). the master continues outputting the serial clock since the start of 8-bit data transfer until the busy signal is deasserted.
chapter 5 peripheral hardware function 213 user s manual u10201ej2v4um00 (a) bus release signal (rel) the bus release signal is asserted when the sb0 or sb1 line goes high while the sck line is high (i.e., when the serial clock is not output). this signal is output by the master. fig. 5-72 bus release signal the slave has hardware that detects the command signal. sck "h" sb0, sb1 the bus release signal indicates that the master is to transmit an address to a slave. the slave has hardware that detects the bus release signal. (b) command signal (cmd) the command signal is asserted when the sb0 or sb1 line goes low while the sck line is high (i.e., when the serial clock is not output). this signal is output by the master. fig. 5-73 command signal sck "h" sb0, sb1
chapter 5 peripheral hardware function 214 user s manual u10201ej2v4um00 (c) address an address is 8-bit data output by the master to select a specific slave from the slaves connected to the bus line. fig. 5-74 address the 8-bit data following the bus release signal and command signal is defined as an address. the slave detects an address by using hardware, and checks whether the 8-bit data coincides with its own specification number (slave address). if the 8-bit data coincides with the slave address, the slave is selected. subsequently, the slave communicates with the master, until the master later unselects the slave. fig. 5-75 selecting slave by address sck a7 a6 a5 a4 a3 a2 a1 a0 12345678 sb0, sb1 address command signal bus release signal master slave 1 unselected slave 2 selected slave 3 unselected slave 4 unselected
chapter 5 peripheral hardware function 215 user s manual u10201ej2v4um00 (d) command and data the master transmits commands to or transmits or receives data to or from the slave it has selected by transmitting an address. fig. 5-76 command sck c7 c6 c5 c4 c3 c2 c1 c0 12345678 sb0, sb1 command command signal fig. 5-77 data the 8-bit data following the command signal is defined as a command. the 8-bit data that does not follow the command signal is defined as data. how to use the command and data can be determined as you like, depending on the communication specified. sck d7 d6 d5 d4 d3 d2 d1 d0 12345678 sb0, sb1 data
chapter 5 peripheral hardware function 216 user s manual u10201ej2v4um00 (e) acknowledge signal (ack) the acknowledge signal is used for confirmation of data reception between the transmitter and receiver sides. fig. 5-78 acknowledge signal the acknowledge signal is a one-shot pulse synchronized with the falling edge of sck after 8-bit data has been transferred, and can be synchronized with arbitrary assertion of sck. the transmitter side checks, after it has transmitted 8-bit data, whether the receiver side returns an acknowledge signal. if the acknowledge signal is not returned for a fixed time after the data has been transmitted, it is judged that the data has not been received correctly. ack sck sb0, sb1 8 9 10 11 ack sck 89 sb0, sb1 (when output in synchronization with 11th sck) (when output in synchronization with 9th sck)
chapter 5 peripheral hardware function 217 user s manual u10201ej2v4um00 (f) busy (busy) and ready (ready) signals the busy signal is output by a slave to inform the master that the slave is preparing for transmission or reception. the ready signal is also output by a slave to inform the master that the slave is now ready for transmission or reception. fig. 5-79 busy and ready signals ack ready sb0, sb1 busy 89 sck in the sbi mode, the slave makes the sb0 (or sb1) line low to inform the master of the busy status. the busy signal is output following the acknowledge signal output by the master or slave. the busy signal is asserted or deasserted in synchronization with the falling edge of sck. the master automatically ends output of serial clock sck when the busy signal is deasserted. the master can start the next transfer when the busy signal has been deasserted and the ready signal is asserted.
chapter 5 peripheral hardware function 218 user s manual u10201ej2v4um00 (3) register setting when the sbi mode is used, the following two registers must be set: serial operation mode register (csim) serial bus interface control register (sbic) (a) serial operation mode register (csim) when the sbi mode is used, set the csim as shown below (for the format of the csim, refer to 5.6.3 (1) serial operation mode register (csim) ). the csim is manipulated by using an 8-bit manipulation instruction. bits 7, 6, and 5 can also be manipulated in 1-bit units. the contents of the csim are cleared to 00h at reset. the shaded portion in the figure indicates the bits used in the three-line serial i/o mode. remark (r) : read only (w) : write only serial interface operation enable/disable bit (w) operation of shift register serial clock counter irqcsi flag so/sb0 and si/sb1 pins shift operation range count operation can be set function in each mode and port 0 function shared csie 1 signal from address comparator (r) coi note clear condition (coi = 0) set condition (coi = 1) note coi can be read before the start of serial transfer and after completion of the serial transfer. an undefined value is read if this bit is read during transfer. the data written to coi by an 8-bit manipulation instruction is ignored. when data of slave address register (sva) and data of shift register do not coincide when data of slave address register (sva) and data of shift register coincide 765432 10 address symbol serial clock select bits (w) serial interface operation mode select bits (w) wake-up function specification bit (w) coincidence signal from address comparator (r) serial interface operation enable/disable bit (w) csim0 csim1 csim3 csim2 csim4 wup coi csie csim fe0h
chapter 5 peripheral hardware function 219 user s manual u10201ej2v4um00 wake-up function specification bit (w) wup 0 sets irqcsi each time serial transfer is completed with sbi mode masked. 1 used only by the slave in sbi mode. irqcsi is set only when an address received by the slave after the bus has been released coincides with the data of the slave register of the slave (wake- up status). sb0 or sb1 goes into a high-impedance state. caution busy is not deasserted if wup is set to 1 while the busy signal is output. in the sbi mode, the busy signal is output after a command to deassert the busy signal has been issued until the next serial clock (sck) falls. before setting wup to 1, be sure to deassert the busy signal and confirm that the sb0 (or sb10 pin has gone high. serial interface operation mode select bit (w) csim4 csim3 csim2 bit order of shift register so pin function si pin function 010sio 7-0 ? xa (msb first) sb0/p02 p03 input (n-ch open-drain) 1 p02 input sb1/p03 (n-ch open-drain i/o) serial clock select bit (w) csim1 csim0 serial clock sck pin mode 0 0 external clock input to sck pin input 0 1 timer/event counter output (to) output 10f x /2 4 (262 khz) note 11f x /2 3 (524 khz) note note ( ): f x = 4.19 mhz
chapter 5 peripheral hardware function 220 user s manual u10201ej2v4um00 (b) serial bus interface control register (sbic) when the sbi mode is used, set sbic as shown below (for the format of sbic, refer to 5.6.3 (2) serial bus interface control register (sbic) ). this register is manipulated by using a bit manipulation instruction. the contents of sbic are cleared to 00h at reset. the shaded portion in the figure indicate the bits used in the three-line serial i/o mode. remark (r) : read only (w) : write only (r/w) : read/write busy enable bit (r/w) bsye 0 <1> disables automatic output of busy signal <2> stops output of busy signal in synchronization with falling edge of sck immediately after clear instruction has been executed 1 outputs busy signal in synchronization with falling of sck following acknowledge signal acknowledge detection flag (r) ackd clear condition (ackd = 0) set condition (ackd = 1) <1> at start of transfer <2> at reset input acknowledge enable bit (r/w) acke 0 disables automatic output of acknowledge signal (output by ackt is enabled) 1 when set before end of transfer ack is output in synchronization with 9th sck when set after end of transfer ack is output in synchronization with sck immediately after execution of set instruction when acknowledge signal (ack) is detected (syn- chronized with falling edge of sck) bus release trigger bit (w) command trigger bit (w) bus release detection flag (r) command detection flag (r) acknowledge trigger bit (w) acknowledge enable bit (r/w) acknowledge detection flag (r) busy enable bit (r/w) 765432 10 relt cmdt cmdd reld ackt acke ackd bsye address sbic fe2h symbol
chapter 5 peripheral hardware function 221 user s manual u10201ej2v4um00 acknowledge trigger bit (w) ackt if this bit is set after end of transfer, ack is output in synchronization with next sck. this bit is automatically cleared to 0 after ack signal has been output. cautions 1. do not set this bit to 1 before the end of serial transfer and during transfer. 2. ackt cannot be cleared by software. 3. to set ackt, clear acke to 0. command detection flag (r) cmdd clear condition (cmdd = 0) set condition (cmdd = 1) <1> when transfer start instruction is executed when command signal (cmd) is detected <2> when bus release signal (rel) is detected <3> when reset signal is input <4> csie = 0 (refer to fig. 5-60 .) bus release detection flag (r) reld clear condition (reld = 0) set condition (reld = 1) <1> when transfer start instruction is executed when bus release signal (rel) is detected <2> when reset signal is input <3> csie = 0 (refer to fig. 5-60 .) <4> when sva and sio do not coincide when address is received command trigger bit (w) cmdt this bit controls output trigger of command signal (cmd). when this bit is set to 1, so latch is cleared to 0. subsequently, the cmdt bit is automatically cleared to 0. caution do not set sb0 (or sb1) during serial transfer. be sure to set it before the start of, or after the end of, transfer. bus release trigger bit (w) relt this bit controls output trigger of bus release signal (rel). when this bit is set to 1, so latch is set to 1. subsequently, the relt bit is automatically cleared to 0. caution do not set sb0 (or sb1) during serial transfer. be sure to set it before the start of, or after the end of, transfer.
chapter 5 peripheral hardware function 222 user s manual u10201ej2v4um00 (4) selecting serial clock the serial clock is selected by using the bits 0 and 1 of the serial operation mode register (csim). the following four types of serial clocks can be selected: table 5-11 selecting serial clock and application (in sbi mode) mode register serial clock csim csim source masking serial clock application 10 0 0 external slave cpu sck 0 1 tout f/f 10f x /2 4 medium-speed serial transfer 11f x /2 3 high-speed serial transfer when the internal system clock is selected, sck is internally stopped when it has been asserted and deasserted eight times. externally, however, counting sck continues until the slave enters the ready status. timing at which shift register can be read/written and serial transfer can be started automatically masked at end of transfer of 8- bit data <1> in operation stop mode (csie = 0) <2> if serial clock is masked after 8-bit serial transfer <3> when sck is high serial transfer at any speed
chapter 5 peripheral hardware function 223 user s manual u10201ej2v4um00 (5) signals figs. 5-80 through 5-85 illustrate the operations of the signals in the sbi mode. table 5-12 lists the signals used in the sbi mode. fig. 5-80 operations of relt, cmdt, reld, and cmdd (master) fig. 5-81 operations of relt, cmdt, reld, and cmdd (slave) sck so iatch relt cmdt cmdd reld sio transfer start command "h" sio sck so iatch reld cmdd 1 2 7 8 d7 d6 d1 d0 transfer start command sio written addresses coincide addresses do not coincide 9 relt (master) cmdt (master)
chapter 5 peripheral hardware function 224 user s manual u10201ej2v4um00 fig. 5-82 operation of ackt (b) when set after completion of transfer sck sb0, sb1 ackt 67 8 9 d2 d1 d0 ack set during this period ack signal is output during 1-clock period immediately after set set after completion of transfer caution do not set ackt before completion of transfer. fig. 5-83 operation of acke (a) when acke = 1 before completion of transfer sck sb0, sb1 acke 1 2789 d7 d6 d2 d1 d0 ack when acke = 1 at this point ack signal is output at 9th clock sck sb0, sb1 acke 7 89 d1 d0 ack 6 d2 when set during this period and acke = 1 at falling of next sck ack signal is output during 1-clock period immediately after set
chapter 5 peripheral hardware function 225 user s manual u10201ej2v4um00 (c) when acke = 0 on completion of transfer (d) if period of acke = 1 is short sck sb0, sb1 acke 12 789 d7 d6 d2 d1 d0 when acke = 0 at this point ack signal not output sck sb0, sb1 acke when set during this period and acke = 0 at falling of sck ack signal not output
chapter 5 peripheral hardware function 226 user s manual u10201ej2v4um00 fig. 5-84 operation of ackd (a) when ack signal is output during period of 9th clock of sck (b) when ack signal is output after 9th clock of sck (c) timing when transfer start command is issued during busy sck sb0, sb1 ackd 789 d1 d0 ack 6 d2 transfer start command sio transfer starts sb0, sb1 ackd 9 sio 78 d1 6 d2 d0 transfer start command transfer starts sck ack ack sck sb0, sb1 ackd 9 transfer start command sio 78 d1 6 d2 d0 d6 d7 busy transfer starts
chapter 5 peripheral hardware function 227 user s manual u10201ej2v4um00 fig. 5-85 operation of bsye sck sb0, sb1 bsye 7 89 ack 6 when bsye = 1 at this point busy when reset during this period and bsye = 0 at falling of sck
chapter 5 peripheral hardware function 228 user s manual u10201ej2v4um00 low-level signal output to sb0 or sb1 during 1-clock period of sck after completion of serial reception table 5-12 signals in sbi mode (1/2) timing chart definition signal name outputting device output condition influence on flag meaning of signal master bus release signal (rel) setting of relt sets reld clears cmdd slave busy signal (busy) master/ slave acknowledge signal (ack) sets cmdd setting of cmdt master command signal (cmd) sets ackd bsye = 1 slave ready signal (ready) [synchronous busy output] rising edge of sb0 or sb1 when sck = 1 subsequently outputs cmd signal to indicate that transmit data is ad- dress i) data transmitted after output of reld signal is address ii) reld signal is not output. transmit data is command falling edge of sb0 or sb1 when sck = 1 [synchronous busy signal] low-level signal output to sb0 or sb1 following acknowledge signal high-level signal output to sb0 or sb1 before and after start of serial transfer <1> acke = 1 <2> setting of ackt <1> bsye = 0 <2> execution of instruction to write data to sio (transfer start command) reception completed serial reception is disabled because processing is in progress serial reception is enabled sck "h" sb0, sb1 sck "h" sb0, sb1 sck d0 ready sb0, sb1 d0 ready sb0, sb1 ack busy busy ack 9
chapter 5 peripheral hardware function 229 user s manual u10201ej2v4um00 8-bit data transferred in synchronization with sck after rel and cmd signals are output serial clock (sck) 8-bit data transferred in synchronization with sck when both rel and cmd signals are not output timing chart definition signal name outputting device output condition influence on flag meaning of signal numeric value to be processed by slave or master device timing of signal output to serial data bus address value of slave device on serial bus command/message to slave device sets irqcsi (rising of 9th clock) note 1 synchronous clock used to output address/command/ data, ack signal, and syn- chronous busy signal. ad- dress/command/data is trans- ferred at first eight clocks table 5-12 signals in sbi mode (2/2) execution of instruction to write data to sio when csie = 1 (serial transfer start command) note 2 notes 1. irqcsi is always set at the rising edge of the 9th clock of sck when wup = 0. when wup = 1, an address is received. only when the address coincides with the value of the slave address register (sva), irqc si is set at the rising edge of the 9th clock of sck. 2. in the busy status, transfer is not started until the ready status is set. 8-bit data transferred in synchronization with sck after only cmd signal is output without rel signal master address (a7-a0) master command (c7-c0) master/ slave data (d7-d0) master sck sb0, sb1 1278910 sck sb0, sb1 1278 rel cmd sck sb0, sb1 1278 cmd sck sb0, sb1 1278
chapter 5 peripheral hardware function 230 user s manual u10201ej2v4um00 (6) pin configuration the configurations of the serial clock pin (sck) and serial data bus pin (sb0 or sb1) are as follows: (a) sck ................... inputs or outputs serial clock <1> master ...... cmos, push-pull output <2> slave ........ schmitt input (b) sb0, sb1 ........... serial data i/o pin n-ch open-drain output and schmitt input for both master and slave because the serial data bus line is of n-ch open-drain output configuration, an external pull-up resistor must be connected to it. fig. 5-86 pin configuration caution because it is necessary to turn off the n-ch transistor when data is received, write ffh to sio in advance. the transistor can be always turned off during transfer. if the wake-up function specification bit (wup) = 1, however, the n-ch transistor is always off. therefore, it is not necessary to write ffh to sio before reception occurs. si so si so (clock input) clock output master device clock input (clock output) serial clock sck sck r l serial data bus sb0, sb1 sb0, sb1 n-ch open-drain n-ch open-drain slave device
chapter 5 peripheral hardware function 231 user s manual u10201ej2v4um00 (7) detection of address coincidence in the sbi mode, the master transmits an address to select a specific slave and then starts communicating with the selected slave. whether the address transmitted to a slave coincides with the address of the slave is detected by the hardware of the slave. for this purpose, the slave is provided with a slave address register (sva). in the wake-up status (wup = 1), the slave sets irqcsi only when the address transmitted from the master coincides with the value set to the sva of the slave. cautions 1. whether a slave is selected or not is detected by detecting coincidence between the address transmitted from the master and the slave address of the slave after the bus has been released (reld = 1). for this coincidence detection, an address coincidence interrupt (irqcsi) that is generated when wup = 1 is usually used. therefore, determine whether a slave is selected or not when wup = 1. 2. to determine whether the slave is selected or not when wup = 0 and without using the interrupt, do not determine the address coincidence, but transmit or receive a command set by program in advance. (8) error detection in the sbi mode, because the status of the serial bus sb0 or sb1 during transmission is also loaded to the shift register sio of the device transmitting data, an error can be detected by the following methods: (a) by comparing sio data before and after transmission if the two data differ from each other, it may be assumed that a transmission error has occurred. (b) by using slave address register (sva) the transmit data is set to sio and sva and transmission is executed. after transmission, the coi bit (coincidence signal from the address comparator) of the serial operation mode register (csim) is tested. if this bit is 1 , the transmission has been completed normally. if it is 0 , it may be assumed that a transmission error has occurred. (9) communication operation in the sbi mode, the master usually selects one of the slave devices with which it is to communicate, by outputting an address onto the serial bus. after the master has determined the slave device, commands and data are transmitted or received between the master and slave. in this way, serial communication is implemented. figs. 5-87 through 5-90 show the timing charts illustrating each data communication. in the sbi mode, the shift register performs its shift operation in synchronization with the falling edge of the serial clock (sck), and the transmit data is latched to the so latch and output from the sb0/p02 or sb1/p03 pin with the msb first. the received data input to the sb0 (or sb1) pin at the rising edge of sck is latched to the shift register.
chapter 5 peripheral hardware function 232 user s manual u10201ej2v4um00 fig. 5-87 address transmission from master device to slave device (wup = 1) 1 2 3 4 5 6 7 8 9 sck pin a7 a6 a5 a4 a3 a2 a1 a0 ack busy sb0, sb1 pin program processing serial transmission irqcsi occurs stops sck hardware operation wup 0 sets ackt program processing sets cmdd irqcsi occurs outputs ack hardware operation sets cmdt sets relt sets cmdt writes sio interrupt processing (preparation for next serial transfer) master device processing (transmitter side) transfer line slave device processing (receiver side) clears cmdd sets cmdd sets reld serial reception outputs busy ready (when sva = sio) address clears busy clears busy sets ackd
chapter 5 peripheral hardware function 233 user s manual u10201ej2v4um00 fig. 5-88 command transmission from master device to slave device sets cmdt 1 2 3 4 5 6 7 8 9 sck pin c7 c6 c5 c4 c3 c2 c1 c0 ack busy sb0, sb1 pin program processing serial transmission irqcsi occurs hardware operation program processing irqcsi occurs hardware operation writes sio interrupt processing (preparation for next serial transfer) master device processing (transmitter side) transfer line sets cmdd serial reception ready reads sio analyzes command slave device processing (receiver side) stops sck sets ackd sets ackt clears busy outputs busy clears busy command outputs ack
chapter 5 peripheral hardware function 234 user s manual u10201ej2v4um00 fig. 5-89 data transmission from master device to slave device 1 2 3 4 5 6 7 8 9 sck pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0, sb1 pin program processing serial transmission irqcsi occurs hardware operation program processing irqcsi occurs hardware operation writes sio interrupt processing (preparation for next serial transfer) master device processing (transmitter side) transfer line serial reception ready data reads sio slave device processing (receiver side) stops sck sets ackd sets ackt clears busy outputs ack outputs busy clears busy
chapter 5 peripheral hardware function 235 user s manual u10201ej2v4um00 fig. 5-90 data transmission from slave device to master device 1 2 3 4 5 6 7 8 9 sck pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0, sb1 pin program processing serial reception irqcsi occurs outputs ack serial reception hardware operation program processing irqcsi occurs hardware operation writes ffh to sio master device processing (receiver side) transfer line serial transmission ready write to sio stops sck 12 ready busy d7 d6 reads sio receive data processing writes ffh to sio writes to sio slave device processing (transmitter side) sets ackt clears busy clears busy sets ackd data outputs busy
chapter 5 peripheral hardware function 236 user s manual u10201ej2v4um00 (10) starting transfer serial transfer is started when the transfer data is set to the shift register (sio), if the following two conditions are satisfied: serial interface operation enable/disable bit (csie) = 1 if the internal serial clock is stopped after 8-bit serial transfer or if sck is high cautions 1. transfer is not started even if csie is set to ??after the data has been written to the shift register. 2. because it is necessary to turn off the n-ch transistor when data is received, write ffh to sio in advance. when the wake-up function specification bit (wup) = 1, however, it is not necessary to write ffh to sio because the n-ch transistor is always off. 3. if data is written to sio while the slave is busy, the data is not lost. when the sb0 (or sb1) input goes high and the slave becomes ready after the slave has been released from the busy status, transfer is started. when 8-bit transfer has been completed, the serial transfer is automatically stopped, and an interrupt request flag (irqcsi) is set. example to transfer the data of the ram addressed by the hl register and at the same time, load the data of sio to the accumulator, and start serial transfer mov xa, @hl ; extracts transmitted data from ram sel mb15 ; or clr1 mbe xch xa, sio ; exchanges transmitted data and received data, and starts transfer (11) notes on sbi mode (a) whether a slave is selected or not is determined by determining coincidence between an address transmitted from the master after the bus has been released (reld = 1) and the slave address of the slave. to determine this coincidence, an address coincidence interrupt (irqcsi) that is generated when wup = 1 is usually used. therefore, determine whether a slave is selected or not by using the slave address when wup = 1. (b) to determine whether a slave is selected or not when wup = 0 and without using the interrupt, do not determine address coincidence but transmit or receive a command set in advance by the program. (c) if wup is set to 1 while the busy signal is output, the busy signal is not deasserted. in the sbi mode, the busy signal is output until the next serial clock (sck) falls after a command that deassert the busy signal has been issued. before setting wup to 1, be sure to deassert the busy signal and confirm that the sb0 (or sb1) pin has gone high.
chapter 5 peripheral hardware function 237 user s manual u10201ej2v4um00 (12) application of sbi mode this paragraph introduces an application example in which serial data communication is executed in the sbi mode. in this example, the pd753036 can operate as both the master and slave cpu on the serial bus. moreover, the master can be changed by a command. (a) serial bus configuration in the application example presented below, it is assumed that the pd753036 is connected to the bus line as one of the devices in the serial bus. the pd753036 uses the serial data bus sb0 (or sb1) and serial clock (sck) pins. fig. 5-91 shows an example of serial bus configuration. fig. 5-91 example of serial bus configuration master cpu pd753036 sb0, sb1 sck slave cpu pd753036 sb0, sb1 sck address 1 slave cpu sb0, sb1 sck address 2 slave ic sb0, sb1 sck address n v dd
chapter 5 peripheral hardware function 238 user s manual u10201ej2v4um00 (b) command description
chapter 5 peripheral hardware function 239 user s manual u10201ej2v4um00
chapter 5 peripheral hardware function 240 user s manual u10201ej2v4um00 <2> write, end, and stop commands the write command writes data to a slave. the amount of data to be written is variable from 1 to 256 bytes. the master specifies the amount of data as a parameter. if 00h is specified as the amount of data, 256 bytes of data is transferred. fig. 5-93 transfer formats of write and end commands remark m : output by master s : output by slave the slave returns ack after it has received the amount of data if the slave has an enough area to store the received data. if the area is insufficient, the slave does not return ack, and an error occurs. the master sends the end command after it has transferred all the data. this command notifies the slave that all the data has been correctly transferred. the slave may receive the end command even before it has received all the data. in this case, all the data the slave has received before it receives the end command is valid. the master compares the contents of sio before and after transfer to check if the data has been correctly output to the bus. if the contents of sio before and after transfer differ, the master issues the stop command to stop data transfer. fig. 5-94 transfer format of stop command remark m : output by master s : output by slave when the slave receives the stop command, it invalidates the 1-byte data it received immediately before reception of the stop command. write m command ack s number of data m data ack sm data data 0 ack sm data data n ack s ..... m command end ack s data m data ack sm command ack s stop checks data error occurs stops data transfer
chapter 5 peripheral hardware function 241 user s manual u10201ej2v4um00 <3> status command this command reads the status of the slave currently selected. fig. 5-95 transfer format of status command remark m : output by master s : output by slave the format of the status returned by the slave is as follows: fig. 5-96 status format of status command the master returns ack when it has received the data from the slave. status m data ack ss command ack s status 7 status 6543210 msb lsb bit indicating whether slave has data to transfer 0: slave has no data to transfer 1: slave has data of 1 byte or more to transfer bit indicating whether slave is ready to receive data 0: slave does not have enough area to store received data 1: slave has area of 1 byte or more to store received data bit indicating occurrence of error 0: no error 1: error occurs during previous transfer bit indicating whether master can be changed 0: master cannot be changed 1: master can be changed all 0
chapter 5 peripheral hardware function 242 user s manual u10201ej2v4um00 <4> reset command this command unselects the slave currently selected. by sending the reset command, the master can unselect all the slaves. fig. 5-97 transfer format of reset command remark m : output by master s : output by slave <5> chgmst command this command gives the mastership to the slave currently selected. fig. 5-98 transfer format of chgmst command remark m : output by master s : output by slave when the slave has received the chgmst command, it decides whether it can receive the mastership, and returns the following data to the master: ffh: master can be changed 00h: master cannot be changed the slave compares the contents of sio before and after transfer of data. if the sio contents do not coincide, the slave does not return ack, and an error occurs. the master returns ack when it has received data. if the received data is ffh, the master starts operating as a slave. after the slave has sent data ffh and received ack from the master, it starts operating as a master. m command ack s reset chgmst m command ack ss data ack s data
chapter 5 peripheral hardware function 243 user s manual u10201ej2v4um00
chapter 5 peripheral hardware function 244 user s manual u10201ej2v4um00 5.6.8 manipulating sck pin output because the sck/p01 pin is provided with an output latch, it can perform static output through software manipulation, in addition to normal clock output. by manipulating the p01 output latch, a chosen number of scks can be set via software. (the so/sb0 and si/ sb1 pins are controlled by the relt and cmdt bits of sbic.) the sck/p01 pin output is manipulated as follows: <1> set the serial operation mode register (csim) (sck pin: output mode). while serial transfer is stopped, sck from the serial clock control circuit is 1. <2> manipulate the p01 output latch by using a bit manipulation instruction. example to output 1 clock to sck/p01 via software sel mb15 ; or clr1 mbe mov xa, #10000011b ; sck (f x /2 3 ), output mode mov csim, xa clr1 0ff0h.1 ; sck/p01 0 set1 0ff0h.1 ; sck/p01 1 fig. 5-100 configuration of sck/p01 pin the p01 output latch is mapped to bit 1 of address ff0h. it is set to 1 when the reset signal is asserted. cautions 1. set the p01 output latch to 1 during normal serial transfer. 2. the address of the p01 output latch cannot be specified as port0.1 , as shown in the example below. directly describe the address (0ff0h.1) as the operand of an instruction. when the instruction is executed, however, it is necessary that mbe = 0 or (mbe = 1, mbs = 15) has been set in advance. must not be used clr port0.1 set1 port0.1 can be used clr1 0ff0h.1 set1 0ff0h.1 to internal circuit p01/sck p01 output latch from serial clock control circuit sck sck pin output mode address ff0h. 1
chapter 5 peripheral hardware function 245 user? manual u10201ej2v4um00 5.7 lcd controller/driver 5.7.1 configuration of lcd controller/driver the pd753036 contains a display controller that generates segment and command signals according to the data of the display memory, and a segment driver and a common driver that can directly drive an lcd panel. fig. 5-101 shows the configuration of the lcd controller/driver.
chapter 5 peripheral hardware function 246 user? manual u10201ej2v4um00 fig. 5-101 block diagram of lcd controller/driver timing controller internal bus 8 display mode register 4 display control register 4 1f8h 3 3 2 2 1 1 0 0 s24/bp0 1f7h 3 3 2 2 1 1 0 0 s23 1ech 3 3 2 2 1 1 0 0 s12 1feh 3 3 2 2 1 1 0 0 s30/bp6 1ffh 3 3 2 2 1 1 0 0 s31/bp7 display data memory multiplexer com3 com2 com1 com0 v lc2 v lc1 v lc0 selector lcd driving mode switching lcd drive voltage control common driver segment driver 4 port 3 out- put latch 10 p31/ sync 8 port mode register group a 10 p30/ lcdcl f lcd
chapter 5 peripheral hardware function 247 user s manual u10201ej2v4um00 5.7.2 function of lcd controller/driver the lcd controller/driver of the pd753036 has the following functions: (a) automatically reads the display data memory by means of dma and generates segment and common signals (b) five display modes selectable <1> static <2> 1/2 duty (2-time division), 1/2 bias <3> 1/3 duty (3-time division), 1/2 bias <4> 1/3 duty (3-time division), 1/3 bias <5> 1/4 duty (4-time division), 1/3 bias (c) four frame frequencies selectable in each display mode (d) up to 20 segment signal outputs (s12-s31) and four command outputs (com0-com3) (e) segment signal outputs (s24-s27, s28-s31) can be used as a bit output port in 4-bit units. (f) dividing resistor for lcd drive power supply can be connected (mask option). each bias method and lcd drive voltage supported current flowing into dividing resistor is cut when display is off. (g) display data memory which is not used for display can be used as ordinary data memory. (h) can operate with subsystem clock table 5-13 shows the maximum number of pixels that can be displayed in each display mode. table 5-13 maximum number of pixels bias method time division common signal used maximum number of pixels static com0 (com1, 2, 3) 20 (20 segments 1 common) note 1 1/2 2 com0, 1 40 (20 segments 2 commons) note 2 3 com0, 1, 2 60 (20 segments 3 commons) note 3 1/3 3 4 com0, 1, 2, 3 80 (20 segments 4 commons) note 4 notes 1. 2 digits of lcd panels of type with 8 segment signals/digit 2. 5 digits of lcd panels of type with 4 segment signals/digit 3. 6 digits of lcd panels of type with 3 segment signals/digit 4. 10 digits of lcd panels of type with 2 segment signals/digit
chapter 5 peripheral hardware function 248 user s manual u10201ej2v4um00 5.7.3 display mode register (lcdm) the display mode register (lcdm) is an 8-bit register that selects a display mode, lcd clock, frame frequency or segment output/bit port output. also, it turns on/off the display output. lcdm is manipulated by an 8-bit memory manipulation instruction. only bit 3 (lcdm3) can also be manipulated by a bit manipulation instruction. all the bits of this register are cleared to 0 when the reset signal is asserted. fig. 5-102 format of display mode register segment output/bit port output selection 0 0 segment output segment output 20 0 0 1 segment output bit port output 16 4 1 0 bit port output segment output 16 4 1 1 bit port output bit port output 12 8 lcd clock selection lcdm5 lcdm4 lcscl note 00f w /2 9 (64 hz) 01f w /2 8 (128 hz) 10f w /2 7 (256 hz) 11f w /2 6 (512 hz) note lcdl is supplied only when the watch timer operates. to use the lcd controller, set bit 2 of the watch mode register wm to 1 . display mode selection lcdm3 lcdm2 lcdm1 lcdm0 number of time divisions bias method 0 display off note 1000 4 1/3 1001 3 1/3 1010 2 1/2 1011 3 1/2 1100 static other than the above setting prohibited note all segment signals are at non-select level. number of segment outputs number of bit port outputs lcdm7 lcdm6 s24-s27 s28-s31 765432 10 lcdm0 lcdm1 lcdm3 lcdm2 lcdm4 lcdm5 lcdm6 lcdm7 address lcdm f8ch symbol
chapter 5 peripheral hardware function 249 user s manual u10201ej2v4um00 frame frequency (hz) lcdcl f w /2 9 f w /2 8 f w /2 7 f w /2 6 (64 hz) (128 hz) (256 hz) (512 hz) static 64 128 256 512 1/2 32 64 128 256 1/3 21 43 85 171 1/4 16 32 64 128 f w = 32.768 khz f w : input clock to watch timer (f x /128 or f xt ) display duty
chapter 5 peripheral hardware function 250 user s manual u10201ej2v4um00 5.7.4 display control register (lcdc) the display control register controls driving of the lcd as follows: enables or disables common and segment outputs cuts current flowing into dividing resistor for lcd drive power supply enables or disables output of synchronization clock (lcdcl) to external segment signal expansion controller/ driver and synchronization signal (sync) selects lcd drive mode according to supply voltage (normal mode or low-voltage mode) normal mode ............ low current consumption low-voltage mode .... operation at low voltage caution to drive lcd at v dd 2.2 v, be sure to set the low-voltage mode. lcdc is manipulated by a 4-bit memory manipulation instruction. all the bits of the display control register are cleared to 0 when the reset signal is asserted. fig. 5-103 format of display control register bit enabling/disabling output of lcdcl and sync signals lcdc2 0 disables output of lcdcl and sync signals 1 enables output of lcdcl and sync signals caution the lcdcl and sync signals are provided for future system expansion. at present, you should disable output of these signals. lcd drive mode select bit vac0 0 normal mode (2.2 v v dd 5.5 v) 1 low-voltage mode (1.8 v v dd 5.5 v) 32 10 lcdc0 vac0 0 lcdc2 address lcdc f8eh symbol
chapter 5 peripheral hardware function 251 user s manual u10201ej2v4um00 display output status selected by lcdc0 and lcdm3 lcdc0 0 1 lcdm3 01 com0-com3 outputs l (display off) s12-s23 outputs l (display off) s24-s31 specified as segment pins s24-s31 specified as bit port pins power supply to off (high impedance) note on (high level) note on (high level) note dividing resistor (bias pin output) note ( ): when the dividing resistor is not used outputs content of bit 0 of corresponding display data memory (bit port function) outputs content of bit 0 of corresponding display data memory (bit port function) outputs content of bit 0 of corresponding display data memory (bit port function) outputs segment signal corresponding to display mode (non-select level out- put, display off) outputs segment signal corresponding to display mode (display on) outputs common signal corresponding to display mode outputs common signal corresponding to display mode
chapter 5 peripheral hardware function 252 user s manual u10201ej2v4um00 5.7.5 display data memory the display data memory is mapped to addresses 1ech through 1ffh. the display data memory is read by the lcd controller/driver by means of dma, independently of the cpu operation. the lcd controller controls segment signals according to the data of the display data memory. when s24 through s31 are used as bit ports, the content of bit 0 of the data written to address 1f8h to 1ffh of the display data memory is output from each bit port output pin. when neither the lcd display is performed nor s24 through s31 are used as port pins, the display data memory can be used as an ordinary data memory area. the display data memory is manipulated in 1- or 4-bit units. it cannot be manipulated in 8-bit units. fig. 5-105 shows the correspondence among the bits of the display data memory, segment output, and bit port output. fig. 5-104 data memory map 000h 100h 0ffh 200h 1ffh 2ffh 1ech data memory 256 4 236 4 20 4 256 4 display data memory bank 0 bank 1 bank 2
chapter 5 peripheral hardware function 253 user s manual u10201ej2v4um00 fig. 5-105 correspondence among display data memory, command, and segment 1f8h 1f9h 1fah 1fbh 1fch 1fdh 1feh 1ffh bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 s24/bp0 s25/bp1 s26/bp2 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 com0 com1 com2 com3 1ech 1edh 1eeh 1efh s12 s13 s14 s15 b 0 b 1 b 2 b 3 address display data memory segment output/bit port output common signal
chapter 5 peripheral hardware function 254 user s manual u10201ej2v4um00 5.7.6 common signal and segment signal each pixel on the lcd panel lights when the potential difference between the common and segment signals corresponding to the pixel rises above a specific level (lcd drive voltage: v lcd ). the light goes off when the potential difference is less than v lcd or when the potential difference becomes zero. because the lcd panel will be degraded if a dc voltage is applied as the common and segment signals, it is driven by an ac voltage. (1) common signal the common signal is selected in the sequence shown in table 5-14 below according to the set number of time divisions. it repeatedly executes its operation at the cycle shown in the table. in the static mode, the same signal is output as com0 through com3. in the case of 2-time division, open the com2 and com3 pins. open the com3 pin in the case of 3-time division. table 5-14 common signal command signal com0 com1 com2 com3 number of time divisions static 2 open open 3 open 4 (2) segment signal twenty segment signals, each corresponding to the 20 locations of the display data memory (1ech through 1ffh) of the data memory, are provided. bits 0, 1, 2, and 3 at each location are automatically read in synchronization with the select timing of com0, com1, com2, and com3, respectively. if the content of each bit is 1, it is converted into a select voltage and output from a segment pin (s12 to s31). if the content of the bit is 0, it is converted into a non-select voltage and output from a segment pin. consequently, you should confirm in what combinations the front-panel electrode (corresponding to segment signals) and rear-panel electrode (corresponding to common signals) of the lcd panel used create display patterns. then, write bit data that corresponds to the pattern to be displayed on a one-to-one basis. because bits 1, 2, and 3 of the display data in the static mode, bits 2 and 3 in the 2-time division mode, and bit 3 in the 3-time division mode are not accessed, these bits can be used for any other purpose besides display.
chapter 5 peripheral hardware function 255 user s manual u10201ej2v4um00 (3) output waveforms of common and segment signals as common and segment signals, voltage levels shown in tables 5-15 through 5-17 are output. only when both the command and segment signals are selected, the voltage reaches to the light level +v lcd / v lcd ; otherwise, the voltage remains at the dark level. table 5-15 lcd drive voltage (static) select non-select v lc0 /v ss v ss /v lc0 v ss /v lc0 + v lcd / v lcd 0 v/0 v table 5-16 lcd drive voltage (1/2 bias) select non-select v lc0 /v ss v ss /v lc0 select v ss /v lc0 + v lcd / v lcd 0 v/0 v non-select v lc1 =v lc2 + v lcd / v lcd v lcd /+ v lcd table 5-17 lcd drive voltage (1/3 bias) select non-select v lc0 /v ss v lc2 /v lc1 select v ss /v lc0 + v lcd / v lcd + v lcd / v lcd non-select v lc1 /v lc2 + v lcd / v lcd + v lcd / v lcd segment signal sn common signal com0 1 2 1 2 1 2 1 2 segment signal sn 1 3 1 3 1 3 1 3 segment signal sn 1 3 1 3 common signal comm common signal comm
chapter 5 peripheral hardware function 256 user s manual u10201ej2v4um00 figs. 5-106 through 5-108 show the common signal waveforms, and fig. 5-109 shows the voltages and phases of the common and segment signals. fig. 5-106 common signal waveform (static) v lc0 v lc1 v lc2 v ss v lcd comm (4-time division) t f = 4 t t : 1 cycle of lcdcl t f : frame cycle v lc0 v lc1 v lc2 v ss v lcd comm (3-time division) t f = 3 t fig. 5-107 common signal waveform (1/2 bias) v lc0 v ss (static) v lcd com0 t f = t t : 1 cycle of lcdcl t f : frame cycle fig. 5-108 common signal waveform (1/3 bias) v lc0 v ss (3-time division) v lcd v lc1, 2 comm t f = 3 t t : 1 cycle of lcdcl t f : frame cycle v lc0 v ss (2-time division) v lcd v lc1, 2 comm t f = 2 t
chapter 5 peripheral hardware function 257 user s manual u10201ej2v4um00 fig. 5-109 voltages and phases of common and segment signals (a) 1/3 bias (b) 1/2 bias (c) static display mode v lc0 v lc1 v lc2 v ss common signal v lcd v lc0 v lc1 v lc2 v ss v lcd segment signal select non-select t: 1 cycle of lcdcl t t v lc0 v lc1, 2 v ss v lcd v lc0 v ss v lcd select non-select t t v lc1, 2 v lc0 v ss common signal v lc0 segment signal select non-select t t v lcd v lcd v ss
chapter 5 peripheral hardware function 258 user s manual u10201ej2v4um00 5.7.7 supplying lcd drive voltages v lc0 , v lc1 , and v lc2 the pd753036 can internally connect dividing resistors to the v lc0 through v lc2 pins to supply power to drive the lcd. this means that an lcd drive voltage corresponding to each bias method can be supplied without an external dividing resistor. in addition, the pd753036 is also provided with a bias pin to support each lcd drive voltage. this pin is externally connected with the v lc0 pin. as the appropriate lcd driving voltage based on the static, 1/2, and 1/3 bias methods, the following values are supplied: table 5-18 voltage supplied as lcd drive voltage bias method no bias lcd (static mode) 1/2 1/3 drive voltage v lc0 v lcd v lcd v lcd v lc1 2/3v lcd 1/2v lcd note 2/3v lcd v lc2 1/3v lcd 1/3v lcd v ss 0 v 0 v 0 v note the v lc1 and v lc2 pins must be externally connected for 1/2 bias. remark when the bias and v lc0 pins are open, v lcd = 3/5 v dd (a dividing resistor must be connected by mask option). when the bias and v lc0 pins are connected, v lcd = v dd . fig. 5-110 (a), (b), and (c) show examples of supplying the lcd drive voltage according to table 5-18. the current flowing into the dividing resistor can be cut by clearing the bit 0 (lcdc0) of the display control register to 0 . controlling on/off of the lcd power supply is effective for preventing a dc voltage from being applied to the lcd when the watch timer operates with the main system clock and when the lcd clock is stopped by the stop instruction (when the system clock is selected). you should clear the bit 0 (lcdc0) of the display control register to 0 immediately before the stop instruction is executed. this will make all the lcd drive power supply the same potential, v ss , and prevent a potential difference between the electrodes of the lcd even when the lcd clock is stopped. if the watch timer operates with the subsystem clock, the lcd display can be continued.
chapter 5 peripheral hardware function 259 user s manual u10201ej2v4um00 fig. 5-110 example of connection of lcd drive power supply (with dividing resistor connected) (a) 1/3 bias and static display mode (b) 1/2 bias (example of v dd = 5 v, v lcd = 3 v) (v dd = 5 v, v lcd = 5 v) (c) 1/3 bias and static display mode (v dd = 5 v, v lcd = 5 v) lcdc0 v dd 2r r v lc0 bias pin r v lc1 r v lc2 v ss v lcd v lcd = v dd pd753036 lcdc0 v dd 2r r v lc0 bias pin r v lc1 r v lc2 v ss v lcd v lcd = v dd pd753036 lcdc0 v dd 2r r v lc0 bias pin r v lc1 r v lc2 v ss v lcd v lcd = 3/5 v dd pd753036
chapter 5 peripheral hardware function 260 user s manual u10201ej2v4um00 fig. 5-111 example of connection of lcd drive power supply (with external dividing resistor connected) (a) static display mode note (b) static display mode (example of v dd = 5 v, v lcd = 5 v) (example of v dd = 5 v, v lcd = 3 v) (c) 1/2 bias (d) 1/3 bias (example of v dd = 5 v, v lcd = 2.5 v) (example of v dd = 5 v, v lcd = 3 v) note always set lcdc0 to 1 (including in the standby mode). lcdc0 v dd v lc0 bias pin v lc1 v lc2 v ss v lcd v lcd = v dd pd753036 lcdc0 v dd 2r 3r v lc0 bias pin v lc1 v lc2 v ss v lcd v lcd = 3/5 v dd pd753036 lcdc0 v dd 2r r v lc0 bias pin v lc1 r v lc2 v ss v lcd v lcd = 1/2 v dd pd753036 lcdc0 v dd 2r r v lc0 bias pin r v lc1 r v lc2 v ss v lcd v lcd = 3/5 v dd pd753036
chapter 5 peripheral hardware function 261 user s manual u10201ej2v4um00 5.7.8 display mode (1) example of static display fig. 5-113 shows the connection between a 3-digit lcd panel with the display pattern shown in fig. 5-112 and the segment (s12 through s31) and common (com0) signals of the pd753036. a display example shown in fig. 5-113 is 123, to which the contents of the data memory (addresses 1ech through 1ffh) correspond. take the first digit 3 ( ) for example. it is necessary to output the select and non-select voltages as shown in table 5-19 at the timing of the common signal com0 to the s12 through s18 pins, according to the display pattern in fig. 5-112. table 5-19 select and non-select voltages of s12-s18 pins (static display example) segment common com0 selected selected selected not selected selected not selected selected therefore, it is evident that 1110101 must be at bit 0 of the display data memory (addresses 1ech through 1f2h). fig. 5-114 shows the lcd drive waveforms of s14, s15, and com0. if the voltage on s14 reaches to the level at which s11 and com0 are selected, an ac square wave of +v lcd / v lcd , which is the level at which the lcd lights, is generated. because the same waveform as com0 is output to com1, 2, and 3, the driving capability can be improved by connecting com0, 1, 2, and 3. fig. 5-112 display pattern and electrode connection of static lcd s12 s13 s14 s15 s16 s17 s18 s14/s21/s28 s18/s25/s31 com0 s13/s20/s27 s16/s23/s29 s12/s19/s26 s15/s22 s17/s24/s30
chapter 5 peripheral hardware function 262 user s manual u10201ej2v4um00 fig. 5-113 example of connecting static lcd panel 1 1 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 0 s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 bit0 bit1 bit2 bit3 com0 com1 com2 com3 timing strobe pd753036 can be short circuited lcd panel data memory address 1 f f h d e f 1 2 3 4 5 6 7 8 9 a b c d e 1 f 0 h 1 f c h
chapter 5 peripheral hardware function 263 user s manual u10201ej2v4um00 fig. 5-114 example of static lcd drive waveform v lc0 v ss com0 t f v lc0 v ss s14 v lc0 v ss s15 + v lcd 0 com0 _ s14 _ v lcd + v lcd 0 com0 _ s15 _ v lcd
chapter 5 peripheral hardware function 264 user s manual u10201ej2v4um00 (2) example of 2-time division display fig. 5-116 shows an example of connection between an 5-digit 2-time division lcd panel having the display pattern shown in fig. 5-115 and the segment (s12 through s31) and common (com0 and 1) signals of the pd753036. in this figure, 123.45 is displayed, to which the contents of the display data memory (addresses 1ech through 1ffh) correspond. take the third digit 3. ( ) for example. it is necessary to output the select and non-select voltages shown in table 5-20 to the s20 through s23 at the timing of each of the common signals com0 and 1, in accordance with the display pattern in fig. 5-115. table 5-20 select and non-select voltages of s20-s23 (example of 2-time division display) segment common com0 selected selected not selected not selected com1 selected selected selected selected at the data memory address corresponding to s23 (1e7h), for example, 10 must be prepared. fig. 5-117 shows an example of the lcd drive waveform between s23 and each common signal. when the voltage on s9 reaches the select level at the select timing of com1, an ac square wave of +v lcd / v lcd , which is the lcd light level, is generated. fig. 5-115 display pattern and electrode connection of 2-time division lcd s20 s21 s22 s23 com0 com1 s n + 1 s n s n + 2 s n + 3
chapter 5 peripheral hardware function 265 user s manual u10201ej2v4um00 fig. 5-116 example of connecting 2-time division lcd panel remark : any data can always be stored because of 2-time division. 1 0 0 1 1 1 0 1 1 0 1 1 0 1 0 0 1 1 1 1 1 0 0 1 0 0 1 1 1 0 1 1 1 0 1 0 0 0 0 0 bit0 bit1 bit2 bit3 timing strobe pd753036 lcd panel data memory address open open s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 com0 com1 com2 com3 1 f f h d e f 1 2 3 4 5 6 7 8 9 a b c d e 1 f 0 h 1 f c h
chapter 5 peripheral hardware function 266 user s manual u10201ej2v4um00 fig. 5-117 example of 2-time division lcd drive waveform (1/2 bias) v lc0 v lc1, 2 v ss com0 t f v lc0 v lc1, 2 v ss com1 v lc0 v lc1, 2 v ss s23 com0 _ s23 + v lcd + 1/2 v lcd 0 _ 1/2 v lcd _ v lcd com1 _ s23 + v lcd + 1/2 v lcd 0 _ 1/2 v lcd _ v lcd
chapter 5 peripheral hardware function 267 user s manual u10201ej2v4um00 (3) example of 3-time division display fig. 5-119 shows an example of connection between an 6-digit 3-time division lcd panel having the display pattern shown in fig. 5-118 and the segment (s12 through s29) and common (com0 through com2) signals of the pd753036. in this figure, 12345.6 is displayed, to which the contents of the display data memory (addresses 1ech through 1fdh) correspond. take the second digit 5. ( ) for example. it is necessary to output the select and non-select voltages shown in table 5-21 to the s15 through s17 at the timing of each of the common signals com0 through com2, in accordance with the display pattern in fig. 5-118. table 5-21 select and non-select voltages of s15-s17 (example of 3-time division display) segment common com0 not selected selected selected com1 selected selected not selected com2 selected selected at the data memory address corresponding to s15 (1efh), for example, 110 must be prepared. fig. 5-120 shows an example of the 1/2 bias method of the lcd drive waveform between s15 and each common signal, and fig. 5-121 shows an example of the 1/3 bias method. when the voltage on s15 reaches the select level at the select timing of com1, and when the voltage on s15 reaches the select level at the select timing of com2, an ac square wave of +v lcd / v lcd , which is the lcd light level, is generated. fig. 5-118 display pattern and electrode connection of 3-time division lcd s15 s16 s17 com1 seg n + 1 seg n + 2 seg n com0 com2
chapter 5 peripheral hardware function 268 user s manual u10201ej2v4um00 fig. 5-119 example of connecting 3-time division lcd panel remark : any data can be stored because the lcd panel has no corresponding segment. : any data can always be stored because of 3-time division. 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 1 0 0 1 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 bit0 bit1 bit2 bit3 timing strobe pd753036 lcd panel data memory address open s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 com0 com1 com2 com3 1 f d h d e f 1 2 3 4 5 6 7 8 9 a b c 1 f 0 h 1 f c h
chapter 5 peripheral hardware function 269 user s manual u10201ej2v4um00 fig. 5-120 example of 3-time division lcd drive waveform (1/2 bias) v lc0 v lc1, 2 v ss com0 t f v lc0 v lc1, 2 v ss com1 v lc0 v lc1, 2 v ss com2 v lc0 v lc1, 2 v ss s15 + v lcd + 1/2 v lcd 0 com0 _ s15 _ 1/2 v lcd _ v lcd + v lcd + 1/2 v lcd 0 _ 1/2 v lcd _ v lcd + v lcd + 1/2 v lcd 0 _ 1/2 v lcd _ v lcd com1 _ s15 com2 _ s15
chapter 5 peripheral hardware function 270 user s manual u10201ej2v4um00 fig. 5-121 example of 3-time division lcd drive waveform (1/3 bias) v lc0 com0 v lc1 v lc2 v ss t f v lc0 com1 v lc1 v lc2 v ss v lc0 com2 v lc1 v lc2 v ss v lc0 s15 v lc1 v lc2 v ss + v lcd com0 _ s15 + 1/3 v lcd 0 _ 1/3 v lcd _ v lcd + v lcd com1 _ s15 + 1/3 v lcd 0 _ 1/3 v lcd _ v lcd + v lcd com2 _ s15 + 1/3 v lcd 0 _ 1/3 v lcd _ v lcd
chapter 5 peripheral hardware function 271 user s manual u10201ej2v4um00 (4) example of 4-time division display fig. 5-123 shows an example of connection between an 10-digit 4-time division lcd panel having the display pattern shown in fig. 5-122 and the segment (s12 through s31) and common (com0 through com3) signals of the pd753036. in this figure, 123456.7890 is displayed, to which the contents of the display data memory (addresses 1ech through 1ffh) correspond. take the 5th digit 6. ( ) for example. it is necessary to output the select and non-select voltages shown in table 5-22 to the s20 and s21 at the timing of each of the common signals com0 through com3, in accordance with the display pattern in fig. 5-122. table 5-22 select and non-select voltages of s20 and s21 (example of 4-time division display) segment common com0 selected selected com1 not selected selected com2 selected selected com3 selected selected at the data memory address corresponding to s20 (1f4h), for example, 1101 must be prepared. fig. 5-124 shows an example of the lcd drive waveform among s20, com0, and com1 signals (waveforms of com2 and com3 are not shown because of the limited space). when the voltage on s20 reaches the select level at the select timing of com0, an ac square wave of +v lcd / v lcd , which is the lcd light level, is generated. fig. 5-122 display pattern and electrode connection of 4-time division lcd s20 s21 com0 com1 com2 com3 seg n seg n + 1
chapter 5 peripheral hardware function 272 user s manual u10201ej2v4um00 fig. 5-123 example of connecting 4-time division lcd panel 1 1 1 0 1 0 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 bit0 bit1 bit2 bit3 timing strobe pd753036 lcd panel data memory address s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 com0 com1 com2 com3 1 f f h d e f 1 2 3 4 5 6 7 8 9 a b c d e 1 f 0 h 1 f c h
chapter 5 peripheral hardware function 273 user s manual u10201ej2v4um00 fig. 5-124 example of 4-time division lcd drive waveform (1/3 bias) v lc0 com0 v lc1 v lc2 v ss t f v lc0 com1 v lc1 v lc2 v ss v lc0 com2 v lc1 v lc2 v ss v lc0 com3 v lc1 v lc2 v ss + v lcd com0 _ s20 + 1/3 v lcd 0 _ 1/3 v lcd _ v lcd + v lcd com1 _ s20 + 1/3 v lcd 0 _ 1/3 v lcd _ v lcd v lc0 s20 v lc1 v lc2 v ss
chapter 5 peripheral hardware function 274 user s manual u10201ej2v4um00 5.8 a/d converter the pd753036 has an analog-to-digital (a/d) converter with eight analog input channels (an0 through an7) and 8-bit accuracy. this a/d converter is of the successive approximation type. 5.8.1 configuration of the a/d converter fig. 5-125 shows the configuration of the a/d converter. fig. 5-125 block diagram of a/d converter aden adm6 adm5 adm4 soc eoc 0 0 an0 an1 an2 an3 an4 an5 an6/p82 an7/p83 av ref aden av ss r/2 r r r r/2 adm + _ 8 8 8 internal bus control circuit multiplexer sample and hold circuit comparator sa register (8) tap decoder series resistor string
chapter 5 peripheral hardware function 275 user s manual u10201ej2v4um00 (1) pins of a/d converter (a) an0-an7 these pins are eight channels of analog signal inputs to the a/d converter; they input analog signals to be converted into digital signals. an6 is multiplexed with p82, and an7, with p83 note . the a/d converter is provided with a sample and hold circuit. during a/d conversion, the analog input voltage is internally retained. note when using an6 or an7, the following setting is necessary before starting a/d conversion. <1> set port 8 to input mode. <2> disconnect the pull-up resistor from port 8. (for details, refer to 5.1 digital i/o port .) caution be sure to keep the input voltages an0 through an7 within the rated range. if a voltage higher than v dd or lower than v ss (even within the range of the absolute maximum ratings) is input, the converted value of that channel becomes ffh, and the converted values of the other channels may be adversely affected. (b) av ref this input inputs a reference voltage ot the a/d converter. the signal input to an0 through an7 is converted into a digital signal based on the voltage applied across av ref and av ss . (c) av ss this is the gnd pin of the a/d converter. always keep this pin at the same potential as v ss .
chapter 5 peripheral hardware function 276 user s manual u10201ej2v4um00 (2) a/d conversion mode register (adm) adm is an 8-bit register that enables conversion, selects analog input channels, starts conversion, and detects end of conversion. this register is set by an 8-bit manipulation instruction. bits 2 (eoc), 3 (soc), and 7 (aden) can be manipulated in 1-bit units. the contents of adm are initialized to 04h when the reset signal is asserted (only eoc is set to 1 and the other bits are cleared to 0 .) fig. 5-126 format of a/d conversion mode register caution a/d conversion is started 2 4 /f x seconds (2.67 s: f x = 6.0 mhz) after soc has been set note (refer to 5.8.2 operation of a/d converter). note 3.81 s at f x = 4.19 mhz analog channel select bit adm6 adm5 0 0 0 0 0 an2 1 an3 1 0 an0 an1 0 1 1 an5 0 an6 an4 adm4 0 1 0 1 0 1 110 an7 111 765432 10 0 0 soc eoc adm4 adm5 adm6 aden address adm fd8h symbol soc a/d conversion is started when this bit is set. this bit is automatically cleared after conversion has ended. conversion start bit end of conversion detection flag eoc 0 1 a/d conversion enable flag aden 0 1 does not use a/d converter uses a/d converter conversion in progress end of conversion analog channel
chapter 5 peripheral hardware function 277 user s manual u10201ej2v4um00 (3) sa register (sa) the sa (successive approximation) register is an 8-bit register that stores the result of a/d conversion. this register can be read by an 8-bit manipulation instruction. this register is a read-only register and therefore, data cannot be written to it nor can its bits be manipulated. the contents of this register are initialized to 7fh when the reset signal is asserted. cautions 1. when a/d conversion is started with bit 3 (soc) of the adm register set to ?? the results of conversion stored in sa are lost, and the contents of sa are undefined, until a new conversion result is stored to the register. 2. if gnd level is input to the av ref pin or a potential higher than av ref is input to an analog input pin, or if a/d conversion is started with aden cleared to 0, ffh is stored to sa. 5.8.2 operation of a/d converter the input analog signal to be converted to a digital signal is specified by the bits 6, 5, and 4 (adm6, 5, and 4) of the a/d conversion mode register. a/d conversion is started when bits 7 (aden) and 3 (soc) of adm are set to 1 (setting aden is necessary only after the reset signal has been asserted). soc is automatically cleared to 0 after it has been set. a/d conversion is executed by hardware by means of successive approximations, and the resulting 8-bit data is stored to the sa register. bit 2 (eoc) of adm is set to 1 when conversion has ended. fig. 5-127 shows the timing chart for a/d conversion.
chapter 5 peripheral hardware function 278 user s manual u10201ej2v4um00 operate the a/d converter in the following procedure: caution after soc has been set, up to 2 4 /f x (2.67 s when f x = 6.0 mhz) note of delay is generated from the start of a/d conversion until eoc is cleared. therefore, test eoc after soc has been set and the time shown in table 5-23 has elapsed. table 5-23 also shows the a/d conversion time. note 3.81 s when f x = 4.19 mhz start an6, 7 used? set port 8 in input mode disconnect pull-up resistor from port 8 enable a/d conversion select analog input channel start a/d conversion wait 2.67 s: f x = 6.0 mhz conversion ends? read a/d conversion result end can be set at the same time ; set aden ; sets adm6, 5, and 4 ; set soc either identify eoc = 1 or wait by software timer read sa register no yes no yes ; ;
chapter 5 peripheral hardware function 279 user s manual u10201ej2v4um00 table 5-23 setting of scc and pcc setting of scc, pcc a/d conversion time wait time until eoc is wait time until a/d conversion scc3 scc0 pcc1 pcc0 tested after setting of soc ends after setting of soc 0000 168/f x seconds no wait 3 machine cycles 01 (28 s: at f x = 6.0 mhz) note 1 machine cycle 11 machine cycles 1 0 2 machine cycles 21 machine cycles 1 1 4 machine cycles 42 machine cycles 01 no wait no wait 1 conversion operation stops note 40.1 s when f x = 4.19 mhz remark : don t care fig. 5-127 timing chart of a/d conversion note 40.1 s when f x = 4.19 mhz previous data undefined conversion result time until start of a/d conversion (2 4 /f x seconds max.) sampling time a/d conversion 168/f x seconds (28 s: when f x = 6.0 mhz) note soc eoc sa register
chapter 5 peripheral hardware function 280 user s manual u10201ej2v4um00 fig. 5-128 shows the correspondence between the analog input voltages and the converted 8-bit digital data. fig. 5-128 relation between analog input voltage and result of a/d conversion (ideal case) 5.8.3 notes on standby mode the a/d converter operates on the main system clock. therefore, it stops in stop mode or halt mode, in which the device operates on the subsystem clock. at this time, however, a current flows into the av ref pin. to reduce the overall power consumption of the system, this current must be cut off. to do so, disable a/d conversion (aden = 0). 5.8.4 use notes (1) an0-an7 input range be sure to keep the input voltages an0 through an7 within the rated range. if a voltage higher than v dd or lower than v ss (even within the range of the absolute maximum ratings) is input, the converted value of that channel is ffh, and the converted values of the other channels may be adversely affected. ffh feh fdh . . . 03h 02h 01h 00h 0 1 2 3 . . . 253 254 255 1 ( av ref ) 256 256 256 256 256 256 analog input voltage result of digital conversion
chapter 5 peripheral hardware function 281 user s manual u10201ej2v4um00 (2) measures against noise to maintain 8-bit accuracy, care must be exercised so that noise is not superimposed on the av ref and an0 through an7 pins. the higher the output impedance of the analog signal input source, the heavier the influence of noise. to reduce noise, therefore, it is recommended that c be externally connected as shown in fig. 5-129. fig. 5-129 handling of analog input pins (3) an6/p82 and an7/p83 pins analog input pins an6 and an7 are respectively multiplexed with input port pins p82 and p83. when selecting an6 or an7 for a/d conversion, set port 8 in the input mode in advance. do not execute an input instruction during conversion; otherwise, the conversion accuracy may drop. if a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the expected result may not be obtained due to coupling noise. therefore, do not apply a digital pulse to such a pin. av ref , an0-an7 av ss v ss c = 100 to 1000 pf v dd pd753036 if there is a possibility that noise higher than v dd or lower than v ss might be superimposed, use a diode with a low v f (0.3 v max.) for clamping.
chapter 5 peripheral hardware function 282 user s manual u10201ej2v4um00 5.9 bit sequential buffer ... 16 bits the bit sequential buffer (bsb) is a special data memory used for bit manipulation. it can manipulate bits by sequentially changing the address and bit specification. therefore, this buffer is useful for processing data with a long bit length in bit units. this data memory is configured of 16 bits and can be addressed by a bit manipulation instruction in the pmem.@l addressing mode. its bits can be indirectly specified by the l register. the processing can be executed by only incrementing or decrementing the l register in a program loop and by moving the specified bit sequentially. fig. 5-130 format of bit sequential buffer 3 2 1 0 bsb3 fc3h l = fh l = ch 3 2 1 0 bsb2 l = bh l = 8h 3 2 1 0 bsb1 l = 7h l = 4h 3 2 1 0 bsb0 l = 3h l = 0h fc2h fc1h fc0h incs l decs l l register symbol bit address remarks 1. the specified bit is moved according to the l register in the pmem.@l addressing mode. 2. bsb can be manipulated at any time in the pmem.@l addressing mode, regardless of the specification by mbe and mbs. the data in this buffer can also be manipulated even in direct addressing mode. by using 1-, 4-, or 8-bit direct addressing mode and pmem.@l addressing mode in combination, 1-bit data can be successively input or output. to manipulate bsb in 8-bit units, the higher and lower 8 bits are manipulated by specifying bsb0 and bsb2. example for serial output of the 16-bit data of buff1, 2 from bit 0 of port 3 clr1 mbe mov xa, buff1 mov bsb0, xa ; sets bsb0, 1 mov xa, buff2 mov bsb2, xa ; sets bsb2, 3 mov l, #0 loop0: skt bsb0, @l ; tests specified bit of bsb br loop1 nop ; dummy (to adjust timing) set1 port3.0 ; sets bit 0 of port 3 br loop2 loop1: clr1 port3.0 ; clears bit 0 of port 3 nop ; dummy (to adjust timing) nop loop2: incs l ; l l + 1 br loop0 ret
283 user? manual u10201ej2v4um00 chapter 6 interrupt and test functions the pd753036 has eight vectored interrupt sources and two test inputs that can be used for various applications. the interrupt control circuit of the pd753036 has unique features and can service interrupts at extremely high speed. (1) interrupt function (a) hardware-controlled vectored interrupt functions that can control acknowledgment of an interrupt by using an interrupt enable flag (ie ) and interrupt master enable flag (ime) (b) any interrupt start address can be set. (c) interrupt nesting function that can specify priority by using an interrupt priority select register (ips) (d) test function of interrupt request flag (irq ) (occurrence of an interrupt can be checked by software.) (e) releases standby mode (the interrupt that is used to release the standby mode can be selected by the interrupt enable flag.) (2) test function (a) checks setting of a test request flag (irq ) via software (b) releases standby mode (the test source that releases the standby mode can be selected by the test enable flag.) 6.1 configuration of interrupt control circuit the interrupt control circuit is configured as shown in fig. 6-1, and each hardware unit is mapped to the data memory space.
chapter 6 interrupt and test functions 284 user? manual u10201ej2v4um00 fig. 6-1 block diagram of interrupt control circuit internal bus 1 4 2 im0 both edge detection circuit edge detection circuit edge detection circuit im1 selec- tor intbt irqbt irq4 irq0 irq1 intcsi irqcsi intt0 irqt0 intt1 irqt1 intt2 irqt2 intw irqw irq2 note int0/p10 int1/p11 int4/p00 im2 rising edge detection circuit selec- tor int2/p12 falling edge detection circuit kr0/p60 kr3/p63 im2 interrupt enable flag (le ) priority control circuit vector table address generation circuit ist0 ime ips decoder standby release signal vrqn ist1 note noise rejection circuit (the standby mode cannot be released when the noise rejection circuit is selected.)
chapter 6 interrupt and test functions 285 user s manual u10201ej2v4um00 6.2 types of interrupt sources and vector table the pd753036 has the following eight interrupt sources and nesting of interrupts can be controlled by software. table 6-1 types of interrupt sources interrupt source internal/external vectored interrupt request signal (vector table address) interrupt priority note inbt (reference time interval signal from ba- sic interval timer/watchdog timer) int4 (detection of both rising and falling edges is valid) int0 (rising edge or falling edge is selected) int1 intcsi (serial data transfer end signal) intt0 (signal indicating coincidence between count register of timer/event counter 0 and modulo register) intt1 (signal indicating coincidence between count register of timer/event counter 1 and modulo register) intt2 (signal indicating coincidence between count register of timer/event counter 2 and modulo register) internal 1 vrq1 (0002h) external external 2 vrq2 (0004h) external 3 vrq3 (0006h) internal 4 vrq4 (0008h) internal 5 vrq5 (000ah) internal 6 vrq6 (000ch) internal note if two or more interrupts occur at the same time, the interrupts are processed according to this priority.
chapter 6 interrupt and test functions 286 user s manual u10201ej2v4um00 fig. 6-2 interrupt vector table the priority column in table 6-1 indicates the priority according to which interrupts are executed if two or more interrupts occur at the same time, or if two or more interrupt requests are kept pending. write the start address of interrupt service to the vector table , and the set values of mbe and rbe during interrupt service. the vector table is set by using an assembler directive (ventn). example setting of vector table of intbt/int4 vent1 mbe=0, rbe=0, gotobt <1> <2> <3> <4> <1> vector table of address 0002 <2> setting of mbe in interrupt service routine <3> setting of rbe in interrupt service routine <4> symbol indicating start address of interrupt service routine caution the vector address set by the ventn (n = 1-6) instruction is 2n. example setting of vector tables of intbt/int4 and intt0 vent1 mbe=0, rbe=0, gotobt vent5 mbe=0, rbe=1, gotot0 mbe mbe mbe mbe mbe mbe address 0002h 0004h 0006h 0008h 000ah 000ch rbe rbe rbe rbe rbe rbe intbt/lnt4 start address (higher 6 bits) intbt/lnt4 start address (lower 8 bits) int0 start address (higher 6 bits) int0 start address (lower 8 bits) int1 start address (higher 6 bits) int1 start address (lower 8 bits) intcsi start address (higher 6 bits) intcsi start address (lower 8 bits) intt0 start address (higher 6 bits) intt0 start address (lower 8 bits) intt1, intt2 start address (higher 6 bits) intt1, intt2 start address (lower 8 bits)
chapter 6 interrupt and test functions 287 user s manual u10201ej2v4um00 6.3 hardware controlling interrupt function (1) interrupt request flag and interrupt enable flag the pd753036 has the following eight interrupt request flags (irq ) corresponding to the respective interrupt sources: int0 interrupt request flag (irq0) int1 interrupt request flag (irq1) int4 interrupt request flag (irq4) bt interrupt request flag (irqbt) serial interface interrupt request flag (irqcsi) timer/event counter 0 interrupt request flag (irqt0) timer/event counter 1 interrupt request flag (irqt1) timer/event counter 2 interrupt request flag (irqt2) each interrupt request flag is set to 1 when the corresponding interrupt request is generated, and is automatically cleared to 0 when the interrupt service is executed. however, because irqbt, irq4 and irqt1, irqt2 share the vector address, these flags are cleared differently from the other flags (refer to 6.6 service of interrupts sharing vector address ). the pd753036 also has eight interrupt enable flags (ie ) corresponding to the respective interrupt request flags. int0 interrupt enable flag (ie0) int1 interrupt enable flag (ie1) int4 interrupt enable flag (ie4) bt interrupt enable flag (iebt) serial interface interrupt enable flag (iecsi) timer/event counter 0 interrupt enable flag (iet0) timer/event counter 1 interrupt enable flag (iet1) timer/event counter 2 interrupt enable flag (iet2) the interrupt enable flag enables the corresponding interrupt when it is 1 , and disables the interrupt when it is 0 . if an interrupt request flag is set and the corresponding interrupt enable flag enables the interrupt, a vectored interrupt (vrqn) occurs. this signal is also used to release the standby mode. the interrupt request flags and interrupt enable flags are manipulated by a bit manipulation or 4-bit manipulation instruction. when a bit manipulation instruction is used, the flags can be directly manipulated, regardless of the setting of mbe. the interrupt enable flags are manipulated by the ei ie and di ie instructions. to test an interrupt request flag, the sktclr instruction is usually used. example ei ie0 ; enables int0 di ie1 ; disables int1 sktclr irqcsi ; skips and clears if irqcsi is 1 when an interrupt request flag is set by an instruction, a vectored interrupt is executed even if an interrupt does not occur, in the same manner as when the interrupt occurs. the interrupt request flags and interrupt enable flags are cleared to 0 when the reset signal is asserted, disabling all the interrupts.
chapter 6 interrupt and test functions 288 user s manual u10201ej2v4um00 table 6-2 signals setting interrupt request flags interrupt request flag signal setting interrupt request flag interrupt enable flag set by reference time interval signal from basic interval/watchdog timer also set by detection of both rising and falling edges of int4/p00 pin input signal set by detection of edge of int0/p10 pin input signal. edge to be detected is selected by int0 edge detection mode register (im0) set by detection of edge of int1/p11 pin input signal. edge to be detected is selected by int1 edge detection mode register (im1) set by serial data transfer end signal from serial interface set by coincidence signal from timer/event counter 0 set by coincidence signal from timer/event counter 1 set by coincidence signal from timer/event counter 2 irqbt irq4 irq0 irq1 irqcsi irqt0 irqt1 irqt2 iebt ie4 ie0 ie1 iecsi iet0 iet1 iet2 (2) interrupt priority select register (ips) the interrupt priority select register selects an interrupt with the higher priority that can be nested. the lower 3 bits of this register are used for this purpose. bit 3 is an interrupt master enable flag (ime) that enables or disables all the interrupts. ips is set by a 4-bit memory manipulation instruction, but bit 3 is set or reset by the ei or di instruction. to change the contents of the lower 3 bits of ips, the interrupt must be disabled (ime = 0). example di ; disables interrupt clr1 mbe mov a, #1011b mov ips, a ; gives higher priority to int1 and enables interrupt when the reset signal is asserted, all the bits of this register are cleared to 0 .
chapter 6 interrupt and test functions 289 user s manual u10201ej2v4um00 fig. 6-3 interrupt priority select register 3210 selects interrupt with higher priority ips0 ips1 ips2 ips3 address ips fb2h symbol 0 does not give high priority to any interrupt 00 vrq1 (intbt/int4) 001 vrq2 (int0) 010 vrq3 (int1) 011 vrq4 (intcsi) 100 vrq5 (intt0) 101 vrq6 (intt1, intt2) 110 1 setting prohibited 11 gives high priority to interrupts shown on left interrupt master enable flag (lme) 0 disables all interrupts and vectored interrupt is not started interrupt is enabled or disabled by corresponding interrupt enable flag 1
chapter 6 interrupt and test functions 290 user s manual u10201ej2v4um00 (3) hardware of int0, int1, and int4 (a) fig. 6-4 (a) shows the configuration of int0, which is an external interrupt input that can be detected at the rising or falling edge depending on specification. int0 also has a noise rejection function which uses a sampling clock (refer to fig. 6-5 i/o timing of noise rejection circuit ). the noise rejection circuit rejects a pulse having a width narrower than 2 cyclesnote of the sampling clock as a noise. however, a pulse having a width wider than one cycle of the sampling clock may be accepted as the interrupt signal depending on the timing of sampling (refer to fig. 6-5 <2> (a) ). a pulse having a width wider than two cycles of the sampling clock is always accepted as the interrupt without fail. int0 has two sampling clocks for selection: f and f x /64. these sampling clocks are selected by using bit 3 (im03) of the int0 edge detection mode register (im0) (refer to fig. 6-6 (a) ). the edge of int0 to be detected is selected by using bits 0 and 1 of im0. fig. 6-6 (a) shows the format of im0. this register is manipulated by a 4-bit manipulation instruction. all the bits of this register are cleared to 0 when the reset signal is asserted, and the rising edge of int0 is specified to be detected. note when sampling clock is : 2t cy when sampling clock is f x /64 : 128/f x cautions 1. even when a signal is input to the int0/p10 pin in the port mode, it is input through the noise rejection circuit. therefore, input a signal having a width wider than two cycles of the sampling clock. 2. when the noise rejection circuit is selected (by clearing im02 to 0), int0 does not operate in the standby mode because it performs sampling by using the clock. therefore, do not select the noise rejection circuit if it is necessary to release the standby mode by int0 (set im02 to 1). (b) fig. 6-4 (b) shows the configuration of int1, which is an external interrupt input that can be specified for detection at the rising or falling edge. the edge to be detected is selected by using the int1 edge detection mode register (im1). fig. 6-6 (b) shows the format of im1. this register is manipulated by a 4-bit manipulation instruction. all the bits of this register are cleared to 0 when the reset signal is asserted, and the rising edge is specified for detection. (c) fig. 6-4 (c) shows the configuration of int4, which is an external interrupt input that can be specified for detection at both the rising and falling edges.
chapter 6 interrupt and test functions 291 user s manual u10201ej2v4um00 fig. 6-4 configuration of int0, int1, and int4 (a) hardware of int0 (b) hardware of int1 internal bus 4 im0 noise rejection circuit int0/p10 selector selector f f x /64 im03 edge detection circuit int0 (irq0 set signal) im00, im01 im02 specifies edge to be detected. selects sampling clock. input buffer internal bus 4 im1 specifies edge to be detected. input buffer edge detection circuit int1 (irq1 set signal) im10 int1/p11 (c) hardware of int4 internal bus input buffer both edge detection circuit int4 (irq4 set signal) int4/p00
chapter 6 interrupt and test functions 292 user s manual u10201ej2v4um00 fig. 6-5 i/o timing of noise rejection circuit l l h h l l l l h l h h l l rejected as noise rejected as noise t smp t smp t smp t smp t smp <1> narrow than sampling cycle (t smp ) int0 shaped output int0 shaped output int0 shaped output int0 shaped output <2> 1 to 2 times wider than sampling cycle (a) (b) <3> more than two times wider than sampling clock "l" "l" remark t smp = t cy or 64/f x
chapter 6 interrupt and test functions 293 user s manual u10201ej2v4um00 fig. 6-6 format of edge detection mode register (a) int0 edge detection mode register (im0) 3210 im00 im01 im02 im03 address im0 fb4h symbol im01 specifies edge to be detected im00 0 rising edge 0 0 falling edge 1 1 both rising and falling edges 0 1 ignored (interrupt request flag is not set) 1 im02 noise rejection circuit select bit 0 selects noise rejection circuit 1 does not select noise rejection circuit samp]ing standby re]ease enabled disabled disabled enabled im03 sampling clock 0 (0.67 s, 1.33 s, 2.67 s, 10.7 s at 6.0 mhz) 1 f x /64 (10.7 s at 6.0 mhz) ? ? (b) int1 edge detection mode register (im1) 3210 im10 0 0 0 address im1 fb5h symbol im10 specifies edge to be detected 0 rising edge 1 falling edge caution when the contents of the edge detection mode register are changed, the interrupt request flag may be set. therefore, you should disable interrupts before changing the contents of the mode register. then, clear the interrupt request flag by using the clr1 instruction to enable the interrupts. if the contents of im0 are changed and the sampling clock of f x /64 is selected, clear the interrupt request flag after 16 machine cycles after the contents of the mode register have been changed.
chapter 6 interrupt and test functions 294 user s manual u10201ej2v4um00 (4) interrupt status flag the interrupt status flags (ist0 and ist1) indicate the status of the processing currently executed by the cpu and are included in psw. the interrupt priority control circuit controls nesting of interrupts according to the contents of these flags as shown in table 6-3. because ist0 and ist1 can be changed by using a 4-bit or bit manipulation instruction, interrupts can be nested with the status under execution changed. ist0 and ist1 can be manipulated in 1-bit units regardless of the setting of mbe. before manipulating ist0 and ist1, be sure to execute the di instruction to disable the interrupt. execute the ei instruction after manipulating the flags to enable the interrupt. ist1 and ist0 are saved to the stack memory along with the other flags of psw when an interrupt is acknowledged, and their statuses are automatically changed one higher. when the reti instruction is executed, the original values of ist1 and ist0 are restored. the contents of these flags are cleared to 0 when the reset signal is asserted. table 6-3 ist1 and ist0 and interrupt service status ist1 ist0 processing by cpu 0 0 status 0 0 1 0 1 status 1 1 0 1 0 status 2 1 1 setting prohibited after interrupt acknowledged ist1 ist0 status of processing under execution interrupt request that can be acknowledged services interrupt with low or high priority interrupt with high priority can be ac- knowledged services interrupt with high priority acknowledging all interrupts is disabled executes normal program all interrupts can be acknowledged
chapter 6 interrupt and test functions 295 user s manual u10201ej2v4um00 6.4 interrupt sequence when an interrupt occurs, it is processed in the procedure illustrated below. fig. 6-7 interrupt service sequence notes 1. ist1 and 0: interrupt status flags (bits 3 and 2 of psw; refer to table 6-3 .) 2. each vector table stores the start address of an interrupt service program and the preset values of mbe and rbe when the interrupt is started. interrupt (int ) occurs sets irq ie set? corresponding vrqn occurs pending until ie is set no yes ime=1 pending until ime is set no is vrqn interrupt with high priority? yes yes note 1 ist1, 0 = 00 or 01 note 1 ist1 , 0 = 00 yes no no if two or more vrqn occur simultaneously, one is selected according to the priority intable 6-1. rest of vrqn pending until service under execution is completed selected vrqn saves contents of pc and psw to stack memory and sets data note 2 to pc, rbe, and mbe in vector table corresponding to started vrqn updates contents of ist0 and 1 to 01 if they are 00, or to 10 if they are 01 resets acknowledged irq (however, if interrupt source shares vector address with other interrupt, refer to 6.6 ) jumps to interrupt service program start address yes no
chapter 6 interrupt and test functions 296 user s manual u10201ej2v4um00 6.5 nesting control of interrupts the pd753036 can nest interrupts by the following two methods: (1) nesting with interrupt having high priority specified this method is the standard nesting method of the pd753036. one interrupt source is selected and nested. an interrupt with the higher priority specified by the interrupt priority select register (ips) can occur when the status of the service under execution is 0 or 1, and the other interrupts (interrupts with the lower priority) can occur when the status is 0 (refer to fig. 6-8 and table 6-3 ). therefore, if you use this method when you wish to nest only one interrupt, operations such as enabling and disabling interrupts while the interrupt is serviced need not to be performed, and the nesting level can be kept to 2. fig. 6-8 nesting of interrupt with high priority interrupt disabled ips set interrupt enabled interrupt with low or high priority occurs interrupt with high priority occurs normal processing (status 0) interrupt service with low or high priority (status 1) interrupt service with high priority (status 2)
chapter 6 interrupt and test functions 297 user s manual u10201ej2v4um00 (2) nesting by changing interrupt status flags nesting can be implemented if the interrupt status flags are changed by program. in other words, nesting is enabled when ist1 and ist0 are cleared to 0, 0 by an interrupt service program, and status 0 is set. this method is used to nest two or more interrupts, or to implement nesting level 3 or higher. before changing ist1 and ist0, disable interrupts by using the di instruction. fig. 6-9 interrupt nesting by changing interrupt status flag interrupt disabled ips set interrupt enabled interrupt with low or high priority occurs interrupt disabled ist changed interrupt enabled interrupt with low or high priority occurs status 1 status 0 status 0 status 1 normal processing (status 0) nesting of one interrupt nesting of two interrupts
chapter 6 interrupt and test functions 298 user s manual u10201ej2v4um00 6.6 service of interrupts sharing vector address because interrupt sources intbt and int4 share vector tables, and intt1 and intt2 do also, you should select one or both of the interrupt sources in the following way: (1) to use one interrupt of the two interrupt sources sharing a vector table, set the interrupt enable flag of the necessary interrupt source to 1 , and clear the interrupt enable flag of the other interrupt source to 0 . in this case, an interrupt request is generated by the interrupt source that is enabled (ie = 1). when the interrupt is acknowledged, the interrupt request flag is reset. (2) to use both interrupts set the interrupt enable flags of both the interrupt sources to 1 . in this case, the interrupt request flags of the two interrupt sources are ored. in this case, if an interrupt request is acknowledged when one or both the interrupt flags are set, the interrupt request flags of both the interrupt sources are not reset. therefore, it is necessary to identify which interrupt source has generated the interrupt by using an interrupt service routine. this can be done by checking the interrupt request flags by executing the sktclr instruction at the beginning of the interrupt service routine. if both the request flags are set when this request flag is tested or cleared, the interrupt request remains even if one of the request flags is cleared. if this interrupt is selected as having the higher priority, nesting service is started by the remaining interrupt request. consequently, the interrupt request not tested is serviced first. if the selected interrupt has the lower priority, the remaining interrupt is kept pending and therefore, the interrupt request tested is serviced first. therefore, an interrupt sharing a vector address with the other interrupt is identified differently, depending whether it has the higher priority, as shown in table 6-4. table 6-4 identifying interrupt sharing vector address with higher priority interrupt is disabled and interrupt request flag of interrupt that takes precedence is tested with lower priority interrupt request flag of interrupt that takes precedence is tested
chapter 6 interrupt and test functions 299 user s manual u10201ej2v4um00 examples 1. to use both intbt and int4 as having the higher priority, and give priority to int4 di sktclr irq4 ; irq4=1? br vsubbt ei reti vsubbt: clr1 irqbt ei reti 2. to use both intbt and int4 as having the lower priority, and give priority to int4 sktclr irq4 ; irq4=1? br vsubbt reti vsubbt: clr1 irqbt reti ...... service routine of int4 ... ......... service routine of intbt ............... ... ......... service routine of int4 service routine of intbt
chapter 6 interrupt and test functions 300 user s manual u10201ej2v4um00 6.7 machine cycles until interrupt service the number of machine cycles required from when an interrupt request flag (irqn) has been set until the interrupt routine is executed is as follows: (1) if irqn is set while interrupt control instruction is executed if irqn is set while an interrupt control instruction is executed, the next one instruction is executed. then three machine cycles of interrupt processing is performed and the interrupt routine is executed. a: sets irqn b: executes next one instruction (1 to 3 machine cycles; differs depending on instruction) c: interrupt service (3 machine cycles) d: executes interrupt routine remarks 1. an interrupt control instruction manipulates the hardware units related to interrupt (address fb h of the data memory). the ei and di instructions are interrupt control instructions. 2. the three machine cycles of interrupt service is the time required to manipulate the stack which will be manipulated when an interrupt is acknowledged. cautions 1. if two or more interrupt control instructions are successively executed, the one instruction following the interrupt control instruction executed last is executed, three machine cycles of interrupt service is performed, and then the interrupt routine is executed. 2. if the di instruction is executed when or after irqn is set (a in the above figure), the interrupt request corresponding to irqn that has been set is kept pending until the ei instruction is executed next time. ab c d interrupt control instruction
chapter 6 interrupt and test functions 301 user s manual u10201ej2v4um00 (2) if irqn is set while instruction other than (1) is executed (a) if irqn is set at the last machine cycle of the instruction under execution in this case, the one instruction following the instruction under execution is executed, three machine cycles of interrupt service is performed, and then the interrupt routine is executed. a: sets irqn b: executes next one instruction (1 to 3 machine cycles; differs depending on instruction) c: interrupt service (3 machine cycles) d: executes interrupt routine caution if the next instruction is an interrupt control instruction, the one instruction following the interrupt control instruction executed last is executed, three machine cycles of interrupt service is performed, and then the interrupt routine is executed. if the di instruction is executed after irqn has been set, the interrupt request corresponding to the set irqn is kept pending. (b) if irqn is set before the last machine cycle of the instruction under execution in this case, three machine cycles of service is performed after execution of the current instruction, and then the interrupt routine is executed. a: sets irqn b: interrupt service (3 machine cycles) c: executes interrupt routine ab c d instruction other than interrupt control instruction c d instruction other than interrupt control instruction a
chapter 6 interrupt and test functions 302 user s manual u10201ej2v4um00 6.8 effective usage of interrupts use the interrupt function effectively as follows: (1) clear mbe to 0 in interrupt service routine. if the memory used in the interrupt routine is allocated to addresses 00h through 7fh, and mbe is cleared to 0 by the interrupt vector table, you can program without having to be aware of the memory bank. if it is necessary to use memory bank 1, save the memory bank select register by using the push bs instruction, and then select memory bank 1. (2) use different register banks for the normal routine and interrupt routine. the normal routine uses register banks 2 and 3 with rbe = 1 and rbs = 2. if the interrupt routine for one nested interrupt, use register bank 0 with rbe = 0, so that you do not have to save or restore the registers. when two or more interrupts are nested, set rbe to 1, save the register bank by using the push br instruction, and set rbs to 1 to select register bank 1. (3) use the software interrupt for debugging. even if an interrupt request flag is set by an instruction, the same operation as when an interrupt occurs is performed. for debugging of an irregular interrupt or debugging when two or more interrupts occur at the same time, the efficiency can be increased by using an instruction to set the interrupt flag. 6.9 application of interrupt to use the interrupt function, first set as follows by the main program: (a) set the interrupt enable flag of the interrupt used (by using the ei ie instruction). (b) to use int0 or int1, select the active edge (set im0 or im1). (c) to use nesting (of an interrupt with the higher priority), set ips (ime can be set at the same time). (d) set the interrupt master enable flag (by using the ei instruction). in the interrupt service program, mbe and rbe are set by the vector table. however, when the interrupt specified as having the higher priority is processed, the register bank must be saved and set. to return from the interrupt service program, use the reti instruction.
chapter 6 interrupt and test functions 303 user s manual u10201ej2v4um00 (1) enabling or disabling interrupt reset . . . <1> ei ie0 ei iet1 <2> ei . . . . . . <3> di ie0 . . . . . . <4> di . . . . . . . . . . . . . . . . <5> disables interrupts enables int0 and intt1 enables intt1 disables interrupts
chapter 6 interrupt and test functions 304 user s manual u10201ej2v4um00 (2) example of using intbt and int0 (falling edge active). not nested (all interrupts have higher priority) <1> all the interrupts are disabled by the reset signal and status 0 is set. rbe = 1 is specified by the reset vector table. the sel sb2 instruction uses register banks 2 and 3. <2> int0 is specified to be active at the falling edge. <3> the interrupt is enabled by the ei, ei ie instruction. <4> the int0 interrupt service program is started at the falling edge of int0. the status is changed to 1, and all the interrupts are disabled. rbe = 0, and register banks 0 and 1 are used. <5> execution returns from the interrupt routine when the reti instruction is executed. the status is returned to 0 and the interrupt is enabled. remark if all the interrupts are used with lower priority as shown in this example, saving or restoring the register bank is not necessary if rbe = 1 and rbs = 2 for the main program and register banks 2 and 3 are used, and rbe = 0 for the interrupt service program and register banks 0 and 1 are used. sel <1> reset int0 <4> rb2 mov mov clr1 <2> a, #1 im0, a irq0 ei ei ei ei . . . . . . . . . . . . . . . . . . . . . . . . . iebt ie0 iet0 <3> status 0 status status 1 reti <5> (int0 service program) ; rbe=1, mbe=0 ; rbe=0
chapter 6 interrupt and test functions 305 user s manual u10201ej2v4um00 (3) nesting of interrupts with higher priority (intbt has higher priority and intt0 and intcsi have lower priority) <1> intbt is specified as having the higher priority by setting of ips, and the interrupt is enabled at the same time. <2> intt0 service program is started when intt0 with the lower priority occurs. status 1 is set and the other interrupts with the lower priority are disabled. rbe = 0 to select register bank 0. <3> intbt with the higher priority occurs. the interrupts are nested. the status is changed to 0 and all the interrupts are disabled. <4> rbe = 1 and rbs = 1 to select register bank 1 (only the registers used may be saved by the push instruction). <5> rbs is returned to 2, and execution returns to the main routine. the status is returned to 1. <1> reset intt0 <2> sel ei ei ei mov mov . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rb2 iebt iet0 iecsi a, #9 ips, a status 0 status 0 status 1 reti
chapter 6 interrupt and test functions 306 user s manual u10201ej2v4um00 (4) executing pending interrupt - interrupt input while interrupts are disabled - <1> the request flag is kept pending even if int0 is set while the interrupts are disabled. <2> int0 service program is started when the interrupts are enabled by the ei instruction. <3> same as <1>. <4> intcsi service program is started when the pending intcsi service program is enabled. reset ei ie0 . . . . . . . . . . . . ei . . . . . . . . . . . . . . . . . . . . ei iecsi . . . . . . . . . . . . . . . . . . . . <2> <1> int0 <4>
chapter 6 interrupt and test functions 307 user s manual u10201ej2v4um00 (5) executing pending interrupt - two interrupts with lower priority occur simultaneously - <1> if int0 and intt0 with the lower priority occur at the same time (while the same instruction is executed), int0 with the higher priority is executed first (intt0 is kept pending). <2> when the int0 service routine is terminated by the reti instruction, the pending intt0 service program is started. reset ei iet0 ei ie0 ei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . int0 intt0 <1>
chapter 6 interrupt and test functions 308 user s manual u10201ej2v4um00 (6) executing pending interrupt - interrupt occurs during interrupt service (intbt has higher priority and intt0 and intcsi have lower priority) - <1> if intbt with the higher priority and intt0 with the lower priority occur at the same time, the service of the interrupt with the higher priority is started. (if there is no possibility that an interrupt with the higher priority will occur while another interrupt with the higher priority is being serviced, di ie is not necessary.) <2> if an interrupt with the lower priority occurs while the interrupt with the higher priority is executed, the interrupt with the lower priority is kept pending. <3> when the interrupt with the higher priority has been serviced, intcsi with the higher priority of the pending interrupts is executed. <4> when the service of intcsi has been completed, the pending intt0 is serviced. reset ei iebt ei iet0 ei iecsi mov a, #9 mov ips, a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . intt0 intbt <1>
chapter 6 interrupt and test functions 309 user s manual u10201ej2v4um00 (7) enabling two nesting of interrupts - intt0 and int0 are nested doubly and intcsi and int4 are nested singly - <1> when an intcsi that does not enable nesting occurs, the intcsi service routine is started. the status is 1. <2> the status is changed to 0 by clearing ist0. intcsi and int4 that do not enable nesting are disabled. <3> when an intt0 that enables nesting occurs, nesting is executed. the status is changed to 1, and all the interrupts are disabled. <4> the status is returned to 1 when intt0 service is completed. <5> the disabled intcsi and int4 are enabled, and execution returns to the main routine. reset intcsi <1> ei ei ei ei ei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iet0 ie0 iecsi ie4 status 0 status 0
chapter 6 interrupt and test functions 310 user s manual u10201ej2v4um00 6.10 test function 6.10.1 types of test sources the pd753036 has two types of test sources. of these, int2 is provided with two types of edge-detection testable inputs. table 6-5 types of test sources test source internal/external int2 (detects rising edge input to int2 or falling external edge of input to kr0-kr7) intw (signal from watch timer) internal 6.10.2 hardware controlling test function (1) test request and test enable flags a test request flag (irq ) is set to 1 when a test request is generated. clear this flat to 0 by software after the test processing has been executed. a test enable flag (ie ) is provided to each test enable flag. when this flag is 1 , the standby release signal is enabled; when it is 0 , the signal is disabled. if both the test request flag and test enable flag are set to 1 , the standby release signal is generated. table 6-6 shows the signals that set the test request flags. table 6-6 test request flag setting signals test request flag test request flag setting signal test enable flag irqw signal from watch timer iew irq2 detection of rising edge of int2/p12 pin input signal or detection ie2 of falling edge of any input to kr0/p60-kr7/p73 pins. edge to be detected is selected by int2 edge detection mode register (im2)
chapter 6 interrupt and test functions 311 user s manual u10201ej2v4um00 (2) hardware of int2 and key interrupts (kr0-kr7) fig. 6-10 shows the configuration of int2 and kr0 through kr7. the irq2 setting signal is output when a specified edge is detected on either of the following two types of pins. which pin is selected is specified by using the int2 edge detection mode register (im2). (a) detection of rising edge of int2 pin input when the rising edge of int2 pin input is detected, irq2 is set. (b) detection of rising edge of any of kr0 through kr7 pin inputs (key interrupt) of kr0 through kr7, select the pin used for interrupt input by using the int2 edge detection mode register (im2). when the rising edge of input to the selected pin is detected, irq2 is set. fig. 6-11 shows the format of im2. im2 is set by a 4-bit manipulation instruction. when the reset signal is asserted, all the bits of this register are cleared to 0 and the rising edge of int2 is specified.
chapter 6 interrupt and test functions 312 user s manual u10201ej2v4um00 fig. 6-10 block diagram of int2 and kr0-kr7 kr7/p73 kr6/p72 kr5/p71 kr4/p70 kr3/p63 kr2/p62 kr1/p61 kr0/p60 int2/p12 internal bus 4 im2 falling edge detection circuit rising edge detection circuit selector int2 (lrq2 set signal) input buffer
chapter 6 interrupt and test functions 313 user s manual u10201ej2v4um00 fig. 6-11 format of int2 edge detection mode register (im2) cautions 1. if the contents of the edge detection mode register are changed, the test request flag may be set. disable the test input before changing the contents of the mode register. then, clear the test request flag by the clr1 instruction and enable the test input. 2. if a low level is input to even one of the pins selected for falling edge detection, irq2 is not set even if the falling edge is input to the other pins. 3210 im20 im21 0 0 address im2 fb6h symbol im21 int2 test source im20 0 specifies rising edge of int2 pin input 0 01 10 11 test input pin int2 (1 pin) kr4-kr7 (4 pins) kr2-kr7 (6 pins) kr0-kr7 (8 pins) specifies falling edge of any of krx pin input
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315 user? manual u10201ej2v4um00 chapter 7 standby function the pd753036 possesses a standby function that reduces the power consumption of the system. this standby function can be implemented in the following two modes: ? stop mode ? halt mode the functions of the stop and halt modes are as follows: (1) stop mode in this mode, the main system clock oscillation circuit is stopped and therefore, the entire system is stopped. the power consumption of the cpu is substantially reduced. moreover, the contents of the data memory can be retained at a low voltage (v dd = 1.8 v min.). this mode is therefore useful for retaining the data memory contents with an extremely low current consumption. the stop mode of the pd753036 can be released by an interrupt request; therefore, the microcontroller can operate intermittently. however, because a certain wait time is required for stabilizing the oscillation of the clock oscillation circuit when the stop mode has been released, use the halt mode if processing must be started immediately after the standby mode has been released by an interrupt request. (2) halt mode in this mode, the operating clock of the cpu is stopped. oscillation of the system clock oscillation circuit continues. this mode does not reduce the power consumption as much as the stop mode, but it is useful when processing must be resumed immediately when an interrupt request is issued, or for an intermittent operation such as a watch operation. in either mode, all the contents of the registers, flags, and data memory immediately before the standby mode is set are retained. moreover, the contents of the output latches and output buffers of the i/o ports are also retained; therefore, the statuses of the i/o ports are processed in advance so that the current consumption of the overall system can be minimized. the following page describes the points to be noted in using the standby mode.
chapter 7 standby function 316 user? manual u10201ej2v4um00 cautions 1. the stop mode can be used only when the system operates with the main system clock (oscillation of the subsystem clock cannot be stopped). the halt mode can be used regardless of whether the system operates with the main system clock or subsystem clock. 2. if the stop mode is set when the lcd controller/driver and watch timer operate with main system clock f x , the operations of the lcd controller/driver and watch timer are stopped. to continue the operations of these, therefore, you should change the operating clock to subsystem clock f xt before setting the stop mode. 3. you can operate the pd753036 efficiently with a low current consumption at a low voltage by selecting the standby mode, cpu clock, and system clock. in any case, however, the time described in 5.2.3 setting of system clock and cpu clock is required until the operation is started with the new clock when the clock has been changed by manipulating the control register. to use the clock selecting function and standby mode in combination, therefore, set the standby mode after the time required for selection has elapsed. 4. to use the standby mode, process so that the current consumption of the i/o ports is minimized. especially, do not open the input port, and be sure to input either low or high level to it.
chapter 7 standby function 317 user? manual u10201ej2v4um00 7.1 setting of and operating status in standby mode table 7-1 operating status in standby mode stop mode halt mode setting instruction stop instruction halt instruction system clock on setting clock generation circuit basic interval timer stops operates (sets irqbt at reference time intervals) note 1 serial interface can operate only when external sck can operate note 1 input is selected as serial clock timer/event counter can operate only when ti0-ti2 input is can operate note 1 selected as count clock watch timer can operate when f xt is selected as can operate count clock lcd controller can operate only when f xt is selected can operate as lcdcl external interrupt int1, 2, and 4 can operate. only int0 cannot operate note 2 cpu stops releasing signal interrupt request signal enabled by interrupt enable flag from hardware units that can operate, or reset signal generation notes 1. cannot operate when the main system clock is stopped. 2. can operate only when the noise rejection circuits not selected by bit 2 of the edge detection mode register (im02 = 1). can be set only when processor oper- ates with main system clock can be set regardless of whether proc- essor operates with main system clock or subsystem clock oscillation of only main system clock is stopped only cpu clock is stopped (oscilla- tion continues) operating status
chapter 7 standby function 318 user? manual u10201ej2v4um00 the stop mode is set by the stop instruction, and the halt mode is set by the halt instruction (the stop and halt instructions respectively set bits 3 and 2 of pcc). be sure to write the nop instruction after the stop and halt instructions. when changing the cpu operating clock by using the lower 2 bits of pcc, a certain time elapses after the bits of pcc have been rewritten until the cpu clock is actually changed, as indicated in table 5-5 maximum time required for changing system clock and cpu clock . to change the operating clock before the standby mode is set and the cpu clock after the standby mode has been released, set the standby mode after the lapse of the machine cycles necessary for changing the cpu clock, after rewriting the contents of pcc. in the standby mode, the data is retained for all the registers and data memory that stop in the standby mode, such as general-purpose registers, flags, mode registers, and output latches. cautions 1. when the stop mode is set, x1 input is internally short-circuited to v ss (gnd potential) to suppress leakage of the crystal oscillation circuit. in a system using an external clock, therefore, do not use the stop mode. 2. reset all the interrupt request flags before setting the standby mode. if there is an interrupt source whose interrupt request flag and interrupt enable flag are both set, the standby mode is released immediately after it has been set (refer to fig. 6-1 block diagram of interrupt control circuit). if the stop mode is set, however, the halt mode is set immediately after the stop instruction has been executed, and the time set by the btm register elapses. then, the normal operation mode is restored.
chapter 7 standby function 319 user? manual u10201ej2v4um00 7.2 releasing standby mode both the stop and halt modes can be released when an interrupt request signal occurs that is enabled by the corresponding interrupt enable flag, or when the reset signal is asserted. fig. 7-1 illustrates how each mode is released. fig. 7-1 releasing standby mode (1/2) (a) releasing stop mode by reset signal (b) releasing stop mode by interrupt note the following two times can be selected by mask option: 2 17 /f x (21.8 ms at 6.0 mhz, 31.3 ms at 4.19 mhz) 2 15 /f x (5.46 ms at 6.0 mhz, 7.81 ms at 4.19 mhz) however, the wait time is fixed to 2 15 /f x because the pd75p3036 has no mask option. remark the broken line indicates acknowledgment of the interrupt request that releases the standby mode. clock stop instruction operation mode stop mode oscillates stops halt mode oscillates wait note operation mode reset signal standby release signal clock stop instruction operation mode stop mode stops halt mode oscillates wait (time set by btm) operation mode oscillates
chapter 7 standby function 320 user s manual u10201ej2v4um00 fig. 7-1 releasing standby mode (2/2) (c) releasing halt mode by reset signal note the following two times can be selected by mask option: 2 17 /f x (21.8 ms at 6.0 mhz, 31.3 ms at 4.19 mhz) 2 15 /f x (5.46 ms at 6.0 mhz, 7.81 ms at 4.19 mhz) however, the wait time is fixed to 2 15 /f x because the pd75p3036 has no mask option. remark the broken line indicates acknowledgment of the interrupt request that releases the standby mode. when the stop mode has been released by an interrupt, the wait time is determined by the setting of btm (refer to table 7-2 ). the time required for the oscillation to stabilize varies depending on the type of the resonator used and the supply voltage when the stop mode has been released. therefore, you should select the appropriate wait time depending on the given conditions, and set btm before setting the stop mode. reset signal clock halt instruction operation mode halt mode wait note operation mode oscillates standby release signal clock halt instruction operation mode halt mode operation mode oscillates (d) releasing halt mode by interrupt
chapter 7 standby function 321 user s manual u10201ej2v4um00 table 7-2 selecting wait time by btm wait time note f x = 6.0 mhz f x = 4.19 mhz 0 0 0 about 2 20 /f x (about 175 ms) about 2 20 /f x (about 250 ms) 0 1 1 about 2 17 /f x (about 21.8 ms) about 2 17 /f x (about 31.3 ms) 1 0 1 about 2 15 /f x (about 5.46 ms) about 2 15 /f x (about 7.81 ms) 1 1 1 about 2 13 /f x (about 1.37 ms) about 2 13 /f x (about 1.95 ms) other than the above setting prohibited note this time does not include the time required to start oscillation after the stop mode has been released. caution the wait time that elapses when the stop mode has been released does not include the time that elapses until the clock oscillation is started after the stop mode has been released (a in fig. 7-2), regardless of whether the stop mode has been released by the reset signal or occurrence of an interrupt. fig. 7-2 wait time after releasing stop mode btm3 btm2 btm1 btm0 v ss stop mode released voltage waveform of x1 pin a
chapter 7 standby function 322 user s manual u10201ej2v4um00 7.3 operation after release of standby mode (1) when the standby mode has been released by the reset signal, the normal reset operation is performed. (2) when the standby mode has been released by an interrupt, whether or not a vector interrupt is executed when the cpu has resumed instruction execution is determined by the content of the interrupt master enable flag (ime). (a) when ime = 0 execution is started from the instruction next to the one that set the standby mode after the standby mode has been released. the interrupt request flag is retained. (b) when ime = 1 a vectored interrupt is executed after the standby mode has been released and then two instructions have been executed. however, if the standby mode has been released by intw or int2 (testable input), the processing same as (a) is performed because no vectored interrupt is generated in this case. 7.4 application of standby mode use the standby mode in the following procedure: <1> detect the cause that sets the standby mode such as an interrupt input or power failure by port input (use of int4 to detect a power failure is recommended). <2> process the i/o ports (process so that the current consumption is minimized). especially, do not open the input port. be sure to input a low or high level to it. <3> specify an interrupt that releases the standby mode. (note that use of int4 is effective. clear the interrupt enable flags of the interrupts that do not release the standby mode.) <4> specify the operation to be performed after the standby mode has been released (manipulate ime depending on whether interrupt service is performed or not). <5> specify the cpu clock to be used after the standby mode has been released. (to change the clock, make sure that the necessary machine cycles elapse before the standby mode is set.) <6> select the wait time to elapse after the standby mode has been released. <7> set the standby mode (by using the stop or halt instruction). by using the standby mode in combination with the system clock selecting function, low current consumption and low-voltage operation can be realized.
chapter 7 standby function 323 user s manual u10201ej2v4um00 (1) application example of stop mode (f x = 6.0 mhz)
chapter 7 standby function 324 user s manual u10201ej2v4um00
chapter 7 standby function 325 user s manual u10201ej2v4um00 (2) application of halt mode (f x = 6.0 mhz)
chapter 7 standby function 326 user s manual u10201ej2v4um00
327 user? manual u10201ej2v4um00 chapter 8 reset function two types of reset signals are used: the external reset signal (reset) and a reset signal from the basic interval timer/watchdog timer. when either of these reset signals is input, an internal reset signal is asserted. fig. 8-1 shows the configuration of the reset circuit. fig. 8-1 configuration of reset circuit reset internal reset signal reset signal from basic interval timer/ watchdog timer wdtm internal bus the pd753036 is reset when the reset signal is asserted, and each hardware unit is initialized as shown in table 8-1. fig. 8-2 shows the timing of the reset operation. fig. 8-2 reset operation by reset signal reset signal halt mode operation mode or standby mode internal reset operation operation mode wait note note the following two times can be selected by the mask option: 2 17 /f x (21.8 ms at 6.0 mhz, 31.3 ms at 4.19 mhz) 2 15 /f x (5.46 ms at 6.0 mhz, 7.81 ms at 4.19 mhz) however, the wait time is fixed to 2 15 /f x because the pd75p3036 has no mask option.
chapter 8 reset function 328 user s manual u10201ej2v4um00 when reset signal asserted in standby mode when reset signal asserted during operation hardware program counter (pc) psw carry flag (cy) skip flags (sk0-sk2) interrupt status flags (ist0, ist1) bank enable flags (mbe, rbe) stack pointer (sp) stack bank select register (sbs) data memory (ram) general-purpose register (x, a, h, l, d, e, b, c) bank select registers (mbs, rbs) counter (bt) mode register (btm) watchdog timer enable flag (wdtm) counter (t0) modulo register (tmod0) mode register (tm0) toe0, tout f/f counter (t1) modulo register (tmod1) mode register (tm1) toe1, tout f/f counter (t2) modulo register (tmod2) high-level period setting modulo register (tmod2h) mode register (tm2) toe2, tout f/f remc, nrz, nrzb tge watch timer mode register (wm) sets lower 6 bits of program memory address 0000h to pc13- pc8, and contents of address 0001h to pc7-pc0 retained 0 0 sets bit 6 of program memory address 0000h to rbe and bit 7 to mbe undefined 1000 retained note retained 0, 0 00h 0 0 0 ffh 0 0, 0 0 ffh 0 0, 0 0 ffh ffh 0 0, 0 0, 0, 0 0 0 same as left undefined 0 0 same as left undefined 1000 undefined undefined 0, 0 00h 0 0 0 ffh 0 0, 0 0 ffh 0 0, 0 0 ffh ffh 0 0, 0 0, 0, 0 0 0 table 8-1 status of each hardware unit after reset (1/2) basic inter- val/watch- dog timer timer/event counter (t0) timer/event counter (t1) timer/event counter (t2) note the data at addresses 0f8h through 0fdh of the data memory are undefined when the reset signal is asserted.
chapter 8 reset function 329 user s manual u10201ej2v4um00 table 8-1 status of each hardware unit after reset (2/2) when reset signal asserted in standby mode when reset signal asserted during operation hardware shift register (sio) operation mode register (csim) sbi control register (sbic) slave address register (sva) processor clock control register (pcc) system clock control register (scc) clock output mode register (clom) suboscillation circuit control register (sos) display mode register (lcdm) display control register (lcdc) interrupt request flag (irq ) interrupt enable flag (ie ) interrupt master enable flag (ime) interrupt priority select register (ips) int0, 1, 2 mode registers (im0, im1, im2) output buffer output latch i/o mode registers (pmga, pmgb, pmgc) pull-up resistor specification register (poga, pogb) retained 0 0 retained 0 0 0 0 0 0 reset (0) 0 0 0 0, 0, 0 off cleared (0) 0 0 undefined 0 0 undefined 0 0 0 0 0 0 reset (0) 0 0 0 0, 0, 0 off cleared (0) 0 0 serial interface clock generation circuit, clock output circuit lcd control- ler/driver digital port bit sequential buffer (bsb0-bsb3) retained undefined interrupt function
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331 user? manual u10201ej2v4um00 chapter 9 writing and verifying prom (program memory) the program memory of the pd75p3036 is a one-time prom or eprom. the memory capacity is as follows: pd75p3036: 16384 words 8 bits to write or verify this prom, the pins shown in table 9-1 are used. note that no address input pins are used and that the address is updated by inputting a clock from the x1 pin. table 9-1 pins used to write or verify program memory pin name function x1, x2 inputs clock to update address when program memory is written or verified. complement of x1 pin is input to x2 pin. md0-md3 (p30-p33) select operation mode when program memory is written or verified p40-p43 (lower 4 bits), input or output 8-bit data when program memory is p50-p53 (higher 4 bits) written or verified v dd applies power supply voltage. supplies 1.8 to 5.5 v for normal operation and +6 v when program memory is written or verified v pp applies program voltage for writing or verifying program memory (usually, v dd potential) cautions 1. only the program memory contents of the pd75p3036kk-t can be erased by lighting ultraviolet rays onto the erasure window. 2. connect the pins not used for writing or verifying the program memory to v ss via pull-down resistor.
chapter 9 writing and verifying prom (program memory) 332 user? manual u10201ej2v4um00 9.1 operation mode for writing/verifying program memory when +6 v is applied to the v dd pin of the pd75p3036 and +12.5 v is applied to the v pp pin, the program memory write/verify mode is set. in this mode, the following operation modes can be selected by using the md0 through md3 pins. table 9-2 operation mode specifies operation mode v dd v pp md0 md1 md2 md3 +6 v +12.5 v h l h l clears program memory ad- dress to 0 l h h h write mode l l h h verify mode h h h program inhibit mode remark : l or h operation mode
chapter 9 writing and verifying prom (program memory) 333 user? manual u10201ej2v4um00 9.2 writing program memory the program memory can be written in the following procedure at high speed: (1) pull down the pins not used to v ss with a resistor. the x1 pin is low. (2) supply 5 v to the v dd and v pp pins. (3) wait for 10 s. (4) set the program memory address 0 clear mode. (5) supply +6 v to v dd and +12.5 v to v pp . (6) set the program inhibit mode. (7) write data in the 1-ms write mode (8) set the program inhibit mode. (9) set the verify mode. if the data have been correctly written, proceed to (10). if not, repeat (7) through (9). (10) additional writing of (number of times data have been written in (7) through (9): x) 1 ms (11) set the program inhibit mode. (12) input a pulse four times to the x1 pin to update the program memory address (by one). (13) repeat (7) through (12) until the last address is written. (14) set the program memory address 0 clear mode. (15) change the voltage applied to the v dd and v pp pins to 5 v. (16) turn off the power supply. steps (2) through (12) above are illustrated below. v pp v dd v pp v dd + 1 v dd v dd x1 p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) data input data output data input write verify additional write address increment repeat x times
chapter 9 writing and verifying prom (program memory) 334 user s manual u10201ej2v4um00 9.3 reading program memory the contents of the program memory can be read in the following procedure: (1) pull down the pins not used to v ss with a resistor. the x1 pin is low. (2) supply 5 v to the v dd and v pp pins. (3) wait for 10 s. (4) set the program memory address 0 clear mode. (5) supply +6 v to v dd and +12.5 v to v pp . (6) set the program inhibit mode. (7) verify mode. data of each address is sequentially output at the cycle in which four clock pulses are input to the x1 pin. (8) set the program inhibit mode. (9) set the program memory address 0 clear mode. (10) change the voltage applied to the v dd and v pp pins to 5 v. (11) turn off the power supply. steps (2) through (9) above are illustrated below. v pp v dd v pp v dd + 1 v dd v dd x1 p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) data output data output "l"
chapter 9 writing and verifying prom (program memory) 335 user s manual u10201ej2v4um00 9.4 erasure ( pd75p3036kk-t only) the data written to the program memory of the pd75p3036kk-t can be erased (to ffh) and new data can be rewritten to it. to erase the data contents, cast a light whose wavelength is shorter than approximately 400 nm onto the erase window. usually, an ultraviolet ray of 254 nm is used. the light intensity and time required to completely erase the data contents are as follows: intensity of ultraviolet ray erasure time: 15 w s/cm 2 min. erasure time: 15 to 20 minutes (with an ultraviolet lamp of 12,000 w/cm 2 . however, the erase time may be extended if the performance of the ultraviolet lamp is degraded or if the erasure window is dirty.) to erase the data, place the ultraviolet lamp at a distance of within 2.5 cm from the erasure window. if a filter is attached to the ultraviolet lamp, remove the filter before casting ultraviolet ray. 9.5 opaque film on erasure window ( pd75p3036kk-t only) to protect the eprom contents from being erased by light other than that of the erasure lamp and to prevent the internal circuit other than eprom from malfunctioning due to light, attach an opaque film the erasure window when the eprom contents must be protected. 9.6 one-time prom screening due to their structure, nec cannot fully test one-time prom products ( pd75p3036gc-3b9, 75p3036gk-be9) before shipment. after the required data has be written, we recommend that the proms be screened by being stored in the high temperature environment shown below, and then verified. storage temperature storage time 125 c 24 hours
336 user s manual u10201ej2v4um00 [memo]
337 user? manual u10201ej2v4um00 chapter 10 mask option 10.1 pin the pins of the pd753036 have the following mask options: table 10-1. selecting mask option of pin pin mask option p40-p43, p50-p53 pull-up resistor can be connected in 1-bit units. v lc0 -v lc2 , bias lcd drive power supplying dividing resistors can be connected to four pins at once. 10.1.1 mask option of p40 through p43 and p50 through p53 p40 through p43 (port 4) and p50 through p53 (port 5) can be connected with pull-up resistors by mask option. the mask option can be specified in 1-bit units. if the pull-up resistor is connected by mask option, ports 4 and 5 go high on reset. if the pull-up resistor is not connected, the ports go into a high-impedance state on reset. the ports 4 and 5 of the pd75p3036 do not have a mask option and is always open. 10.1.2 mask option of v lc0 through v lc2 dividing resistors can be connected to the v lc0 through v lc2 pins (lcd drive power supply) and bias pin (external dividing resistor cutting pin) by mask option. therefore, lcd drive power can be supplied without an external dividing resistor according to each bias (for details, refer to 5.7.7 supplying lcd drive voltages v lc0 , v lc1 , and v lc2 ). the following three mask options can be selected. <1> no dividing resistor is connected. <2> a 10-k ? (typ.) dividing resistor is connected. <3> a 100-k ? (typ.) dividing resistor is connected. the mask option is specified for the v lc0 through v lc2 and bias pins at once and cannot be specified in 1-pin units. the bias pin goes low on reset when the dividing resistor is connected to this pin by mask option. when the dividing resistor is not connected, the bias pin goes into a high-impedance state on reset. the pd75p3036 does not have mask option, and cannot be connected with dividing resistors. connect external dividing resistors to the pd75p3036, if necessary. 10.2 mask option of standby function the standby function of the pd753036 allows you to select wait time by using a mask option. the wait time is required for the cpu to return to the normal operation mode after the standby function has been released by the reset signal (for details, refer to 7.2 standby mode release ). the following two wait times can be selected: <1> 2 17 /f x (21.8 ms: f x = 6.0 mhz, 31.3 ms: f x = 4.19 mhz) <2> 2 15 /f x (5.46 ms: f x = 6.0 mhz, 7.81 ms: f x = 4.19 mhz) the pd75p3036 does not have mask options and their wait times are fixed to 2 15 /f x .
chapter 10 mask option 338 user? manual u10201ej2v4um00 10.3 subsystem clock feedback resistor mask options with the mask option settings, you can choose whether or not to use the feedback resistor in the subsystem clock of the pd753036. <1> feedback resistor can be used (switched on or off via software) <2> feedback resistor cannot be used (switched out in hardware) to use the feedback resistor after selecting <1>, set sos.0 to 0 via software, and the feedback resistor is turned on (for details, refer to 5.2.2 (6) suboscillation circuit control register (sos) ). when using the subsystem clock, select <1>. in the pd75p3036, there is no mask option setting, and the feedback resistor can always be used.
339 user? manual u10201ej2v4um00 chapter 11 instruction set the instruction set of the pd753036 is based on the instruction set of the 75x series and therefore, maintains compatibility with the 75x series, but has some improved features. they are: (1) bit manipulation instructions for various applications (2) efficient 4-bit manipulation instructions (3) 8-bit manipulation instructions comparable to those of 8-bit microcontrollers (4) geti instruction reducing program size (5) string-effect and base number adjustment instructions enhancing program efficiency (6) table reference instructions ideal for successive reference (7) 1-byte relative branch instruction (8) easy-to-understand, well-organized nec? standard mnemonics for the addressing modes applicable to data memory manipulation and the register banks valid for instruction execution, refer to 3.2 bank configuration of general-purpose registers . 11.1 unique instructions this section describes the unique instructions of the pd753036? instruction set. 11.1.1 geti instruction the geti instruction converts the following instructions into 1-byte instructions: (a) subroutine call instruction to 16k-byte space (0000h-3fffh) (b) branch instruction to 16-byte space (0000h-3fffh) (c) any 2-byte, 2-machine cycle instruction (except brcb and callf instructions) (c) combination of two 1-byte instructions the geti instruction references a table at addresses 0020h through 007fh of the program memory and executes the referenced 2-byte data as an instruction of (a) to (d). therefore, 48 types of instructions can be converted into 1-byte instructions. if instructions that are frequently used are converted into 1-byte instructions by using this geti instruction, the number of bytes of the program can be substantially decreased.
chapter 11 instruction set 340 user? manual u10201ej2v4um00 11.1.2 bit manipulation instruction the pd753036 has reinforced bit test, bit transfer, and bit boolean (and, or, and xor) instruction, in addition to the ordinary bit manipulation (set and clear) instructions. the bit to be manipulated is specified in the bit manipulation addressing mode. three types of bit manipulation addressing modes can be used. the bits manipulated in each addressing mode are shown in table 11-1. table 11-1 types of bit manipulation addressing modes and specification range fmem. bit rbe, mbe, ist1, ist0, scc, fb0h-fbfh ie , irq port0-8 ff0h-fffh pmem. @l bsb0-3, port0, 4 fc0h-fffh @h+mem. bit all peripheral hardware units that can be manipulated bitwise remarks 1. : 0, 1, 2, 4, bt, t0, t1, t2, w, csi 2. mb = mbe . mbs 11.1.3 string-effect instruction the pd753036 has the following two types of string-effect instructions: (a) mov a, #n4 or mov xa, #n8 (b) mov hl, #n8 ?tring effect?means locating these two types of instructions at contiguous addresses. example a0: mov a, #0 a1: mov a, #1 xa7: mov xa, #07 when string-effect instructions are arranged as shown in this example, and if the address executed first is a0, the two instructions following this address are replaced with the nop instructions. if the address executed first is a1, the following one instruction is replaced with the nop instruction. in other words, only the instruction that is executed first is valid, and all the string-effect instructions that follow are processed as nop instructions. by using these string-effect instructions, constants can be efficiently set to the accumulator (a register or register pair xa) and data pointer (register pair hl). addressing range of bit that can be manipulated peripheral hardware that can be manipulated addressing all bits of memory bank specified by mb that can be manipulated bitwise
chapter 11 instruction set 341 user? manual u10201ej2v4um00 11.1.4 base number adjustment instruction some application requires that the result of addition or subtraction of 4-bit data (which is carried out in binary number) be converted into a decimal number or into a number with a base of 6, such as time. therefore, the pd753036 is provided with base number adjustment instructions that adjusts the result of addition or subtraction of 4-bit data into a number with any base. (1) base adjustment of result of addition where the base number to which the result of addition executed is to be adjusted is m, the contents of the accumulator and memory are added in the following combination, and the result is adjusted to a number with a base of m: adds a, #16-m addc a, @hl ; a, cy a + (hl) + cy adds a, #m occurrence of an overflow is indicated by the carry flag. if a carry occurs as a result of executing the addc a, @hl instruction, the adds a, #n4 instruction is skipped. if a carry does not occur, the adds a, #n4 instruction is executed. at this time, however, the skip function of the instruction is disabled, and the following instruction is not skipped even if a carry occurs as a result of addition. therefore, a program can be written after the adds a, #n4 instruction. example to add accumulator and memory in decimal adds a, #6 addc a, @hl ; a, cy a + (hl) + cy adds a, #10 (2) base adjustment of result of subtraction where the base number into which the result of subtraction executed is to be adjusted is m, the contents of memory (hl) are subtracted from those of the accumulator in the following combination, and the result of subtraction is adjusted to a number with a base of m: subc a, @hl adds a, #m occurrence of an underflow is indicated by the carry flag. if a borrow does not occur as a result of executing the subc a, @hl instruction, the following adds a, #n4 instruction is skipped. if a borrow occurs, the adds a, #n4 instruction is executed. at this time, the skip function of this instruction is disabled, and the following instruction is not skipped even if a carry occurs as a result of addition. therefore, a program can be written after the adds a, #n4 instruction.
chapter 11 instruction set 342 user? manual u10201ej2v4um00 11.1.5 skip instruction and number of machine cycles required for skipping the instruction set of the pd753036 configures a program where instructions may be or may not be skipped if a given condition is satisfied. if a skip condition is satisfied when a skip instruction is executed, the instruction next to the skip instruction is skipped and the instruction after next is executed. when a skip occurs, the number of machine cycles required for skipping is: (a) if the instruction that follows the skip instruction (i.e., the instruction to be skipped) is a 3-byte instruction (br !addr, bra !addr1, call !addr, or calla !addr1 instruction): 2 machine cycles (b) instruction other than (a): 1 machine cycle 11.2 instruction set and operation (1) operand representation and description describe an operand in the operand field of each instruction according to the operand description method of the instruction (for details, refer to ra75x assembler package user? manual - language (eeu-1363) . if two or more operands are shown, select one of them. the uppercase letters, +, and ?are keywords and must be described as is. the symbols of register flags can be described as labels, instead of mem, fmem, pmem, and bit. (however, the number of labels described for fmem and pmem are limited. for details, refer to table 3-1 addressing modes and fig. 3-7 pd753036 i/o map ).
chapter 11 instruction set 343 user? manual u10201ej2v4um00 representation description reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp' xa, bc, de, hl, xa', bc', de', hl' rp'1 bc, de, hl, xa', bc', de', hl' rpa hl, hl+, hl? de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem immediate data fb0h-fbfh, ff0h-fffh or label pmem immediate data fc0h-fffh or label addr immediate data 0000h-3fffh or label addr1 immediate data 0000h-3fffh or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr immediate data 20h-7fh (where bit0 = 0) or label portn port0-port8 ie iebt, iet0-iet2, ie0-ie2, ie4, iecsi, iew rbn rb0-rb3 mbn mb0, mb1, mb2, mb15 note mem can be described only for an even address for 8-bit data processing.
chapter 11 instruction set 344 user? manual u10201ej2v4um00 (2) legend for explanation of operation a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa : expansion register pair (xa? bc : expansion register pair (bc? de : expansion register pair (de? hl : expansion register pair (hl? pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0-8) ime : interrupt master enable flag ips : interrupt priority select register ie : interrupt enable flag rbs : register bank select flag mbs : memory bank select flag pcc : processor clock control register . : address or bit delimiter ( ) : contents addressed by h : hexadecimal data
chapter 11 instruction set 345 user? manual u10201ej2v4um00 *1 mb = mbe . mbs (mbs = 0-2, 15) *2 mb = 0 *3 mbe = 0 : mb = 0 (00h-7fh) mb = 15 (f80h-fffh) mbe = 1 : mb = mbs (mbs = 0-2, 15) *4 mb = 15, fmem = fb0h-fbfh, ff0h-fffh *5 mb = 15, pmem = fc0h-fffh *6 addr = 0000h-3fffh *7 addr, addr1 = (current pc) ?15 to (current pc) ? (current pc) + 2 to (current pc) +16 *8 caddr = 0000h-0fffh (pc 13, 12 = 00b) or 1000h-1fffh (pc 13, 12 = 01b) or 2000h-2fffh (pc 13, 12 = 10b) or 3000h-3fffh (pc 13, 12 = 11b) *9 faddr = 000h-07ffh *10 taddr = 0020h-007fh *11 addr1 = 0000h-3fffh (3) symbols in addressing area field remarks 1. mb indicates a memory bank that can be accessed. 2. in *2, mb = 0 regardless of mbe and mbs. 3. in *4 and *5, mb = 15 regardless of mbe and mbs. 4. *6 through *11 indicate areas that can be addressed. data memory addressing program memory addressing .
chapter 11 instruction set 346 user? manual u10201ej2v4um00 (4) explanation for machine cycle field s indicates the number of machine cycles required for an instruction with skip to execute the skip operation. the value of s varies as follows: when skip is executed .............................................................................. s = 0 when 1- or 2-byte instruction is skipped ................................................. s = 1 when 3-byte instructionnote is skipped .................................................. s = 2 note 3-byte instructions: br !addr, bra !addr1, call !addr, calla !addr1 caution the geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle of cpu clock (=t cy ), and four times can be set by pcc (refer to fig. 5-12 format of processor clock control register ).
chapter 11 instruction set 347 user? manual u10201ej2v4um00 transfer mov a, #n4 1 1 a n4 string effect a reg1, #n4 2 2 reg1 n4 xa, #n8 2 2 xa n8 string effect a hl, #n8 2 2 hl n8 string effect b rp2, #n8 2 2 rp2 n8 a, @hl 1 1 a (hl) *1 a, @hl+ 1 2 + s a (hl), then l l + 1 *1 l = 0 a, @hl 1 2 + s a (hl), then l l ?1 *1 l = fh a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 @hl, a 1 1 (hl) a*1 @hl, xa 2 2 (hl) xa *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 mem, a 2 2 (mem) a*3 mem, xa 2 2 (mem) xa *3 a, reg 2 2 a reg xa, rp' 2 2 xa rp' reg1, a 2 2 reg1 a rp'1, xa 2 2 rp'1 xa xch a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2 + s a ? (hl), then l l + 1 *1 l=0 a, @hl 1 2 + s a ? (hl), then l l ?1 *1 l=fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 a, reg1 1 1 a ? reg1 xa, rp' 2 2 xa ? rp' machine cycle instructions mnemonic operand bytes operation skip condition addressing area
chapter 11 instruction set 348 user? manual u10201ej2v4um00 machine cycle instructions mnemonic operand bytes operation skip condition addressing area movt xa, @pcde 1 3 xa (pc 13-8 + de) rom xa, @pcxa 1 3 xa (pc 13-8 + xa) rom xa, @bcde note 1 3 xa (b 1, 0 + cde) rom *6 xa, @bcxa note 1 3 xa (b 1, 0 + cxa) rom *6 bit transfer mov1 cy, fmem.bit 2 2 cy (fmem.bit) *4 cy, pmem.@l 2 2 cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy (h + mem 3-0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) cy *4 pmem.@l, cy 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy *5 @h+mem.bit, cy 2 2 (h + mem 3-0 .bit) cy *1 operation adds a, #n4 1 1 + s a a + n4 carry xa, #n8 2 2 + s xa xa + n8 carry a, @hl 1 1 + s a a + (hl) *1 carry xa, rp' 2 2 + s xa xa + rp' carry rp'1, xa 2 2 + s rp'1 rp'1 + xa carry addc a, @hl 1 1 a, cy a + (hl) + cy *1 xa, rp' 2 2 xa, cy xa + rp' + cy rp'1, xa 2 2 rp', cy rp'1 + xa + cy subs a, @hl 1 1 + s a a ?(hl) *1 borrow xa, rp' 2 2 + s xa xa ?rp' borrow rp'1, xa 2 2 + s rp'1 rp'1 ?xa borrow subc a, @hl 1 1 a, cy a ?(hl) ?cy *1 xa, rp' 2 2 xa, cy xa ?rp' ?cy rp'1, xa 2 2 rp'1, cy rp'1 ?xa ?cy and a, #n4 2 2 a a n4 a, @hl 1 1 a a (hl) *1 xa, rp' 2 2 xa xa rp' rp'1, xa 2 2 rp'1 rp'1 xa or a, #n4 2 2 a a n4 a, @hl 1 1 a a (hl) *1 xa, rp' 2 2 xa xa rp' rp'1, xa 2 2 rp'1 rp'1 xa xor a, #n4 2 2 a a n4 a, @hl 1 1 a a (hl) *1 xa, rp' 2 2 xa xa rp' rp'1, xa 2 2 rp'1 rp'1 xa note only the lower 2 bits of the b register is valid. table reference
chapter 11 instruction set 349 user? manual u10201ej2v4um00 rorc a 1 1 cy a 0 , a 3 cy, a n? a n not a22a a incs reg 1 1 + s reg reg + 1 reg = 0 rp1 1 1 + s rp1 rp1 + 1 rp1 = 00h @hl 2 2 + s (hl) (hl) + 1 *1 (hl) = 0 mem 2 2 + s (mem) (mem) + 1 *3 (mem) = 0 decs reg 1 1 + s reg reg ?1 reg = fh rp' 2 2 + s rp' rp' ?1 rp' = ffh comparison ske reg, #n4 2 2 + s skip if reg = n4 reg = n4 @hl, #n4 2 2 + s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1 + s skip if a = (hl) *1 a = (hl) xa, @hl 2 2 + s skip if xa = (hl) *1 xa = (hl) a, reg 2 2 + s skip if a = reg a = reg xa, rp' 2 2 + s skip if xa = rp' xa = rp' set1 cy 1 1 cy 1 clr1 cy 1 1 cy 0 skt cy 1 1 + s skip if cy = 1 cy = 1 not1 cy 1 1 cy cy set1 mem.bit 2 2 (mem.bit) 1*3 fmem.bit 2 2 (fmem.bit) 1 *4 pmem. @l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) 1*5 @h+mem.bit 2 2 (h + mem 3-0 .bit) 1*1 clr1 mem.bit 2 2 *3 fmem.bit 2 2 *4 pmem.@l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) 0*5 @h+mem.bit 2 2 (h + mem 3-0 .bit) 0*1 skt mem.bit 2 2 + s skip if(mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2 + s skip if(mem.bit) = 1 *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if(pmem 7-2 + l 3-2 .bit(l 1-0 )) = 1 *5 (pmem.@l) = 1 @h+mem.bit 2 2 + s skip if(h + mem 3-0 .bit) = 1 *1 (@h + mem.bit) = 1 skf mem.bit 2 2 + s skip if(mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2 + s skip if(fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@l 2 2 + s skip if(pmem 7-2 + l 3-2 .bit(l 1-0 )) = 0 *5 (pmem.@l) = 0 @h+mem.bit 2 2 + s skip if(h + mem 3-0 .bit) = 0 *1 (@h + mem.bit) = 0 sktclr fmem.bit 2 2 + s skip if(fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if(pmem 7-2 + l 3-2 .bit(l 1-0 )) = 1 and clear *5 (pmem.@l) = 1 @h+mem.bit 22 + s skip if(h + mem 3-0 .bit) = 1 and clear *1 (@h + mem.bit) = 1 machine cycle instructions mnemonic operand bytes operation skip condition addressing area accumulator manipulation increment/ decrement memory bit manipula- tion carry flag manipula- tion (mem.bit) 0 (fmem.bit) 0
chapter 11 instruction set 350 user? manual u10201ej2v4um00 machine cycle instructions mnemonic operand bytes operation skip condition addressing area and1 cy, fmem.bit 2 2 cy cy (fmem.bit) *4 cy, pmem.@l 2 2 cy cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h + mem.bit 2 2 cy cy (h + mem 3-0 .bit) *1 or1 cy, fmem.bit 2 2 cy cy (fmem.bit) *4 cy, pmem.@l 2 2 cy cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h + mem.bit 22 cy cy (h + mem 3-0 .bit) *1 xor1 cy, fmem.bit 2 2 cy cy (fmem.bit) *4 cy, pmem.@l 2 2 cy cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h + mem.bit 22 cy cy (h + mem 3-0 .bit) *1 branch br note1 addr pc 13-0 addr *6 optimum instruction is selected by assembler from following: br !addr brcb !caddr br $addr1 addr1 pc 13-0 addr1 *11 optimum instruction is selected by assembler from following: br !addr bra !addr1 brcb !caddr br $addr1 !addr 3 3 pc 13-0 addr *6 $addr 1 2 pc 13-0 addr *7 $addr1 1 2 pc 13-0 addr1 pcde 2 3 pc 13-0 pc 13-8 + de pcxa 2 3 pc 13-0 pc 13-8 + xa bcde note2 23pc 13-0 b 1, 0 + cde *6 bcxa note2 23pc 13-0 b 1, 0 + cxa *6 bra note1 !addr1 3 3 pc 13-0 addr1 *11 brcb !caddr 2 2 pc 13-0 pc 13, 12 + caddr 11-0 *8 notes 1. the shaded portion is supported only in the mkii mode. 2. only the lower 2 bits of the b register is valid. memory bit manipula- tion
chapter 11 instruction set 351 user? manual u10201ej2v4um00 machine cycle instructions mnemonic operand bytes operation skip condition addressing area calla note !addr1 3 3 (sp?) (sp?) (sp?) (sp?) 0, 0, pc 13-0 *11 (sp?) , , mbe, rbe pc 13-0 addr1, sp sp ?6 call note !addr 3 3 (sp?) (sp?) (sp?) pc 11-0 *6 (sp?) mbe, rbe, pc 13 , pc 12 pc 13-0 addr, sp sp ?4 4 (sp?) (sp?) (sp?) (sp?) 0, 0, pc 13-0 (sp?) , , mbe, rbe pc 13-0 addr, sp sp ?6 callf note !faddr 2 2 (sp?) (sp?) (sp?) pc 11-0 *9 (sp ?3) mbe, rbe, pc 13 , pc 12 pc 13-0 000 + faddr, sp sp ?4 3 (sp?) (sp?) (sp?) (sp?) 0, 0, pc 13-0 (sp ?2) , , mbe, rbe pc 13-0 000 + faddr, sp sp ?6 ret note 13 mbe, rbe, pc 13 , pc 12 (sp + 1) pc 11-0 (sp) (sp + 3) (sp + 2), sp sp + 4 , , mbe, rbe (sp + 4) 0, 0, pc 13 , pc 12 (sp + 1) pc 11-0 (sp) (sp + 3) (sp + 2), sp sp + 6 rets note 13 + s mbe, rbe, pc 13 , pc 12 (sp + 1) unconditional pc 11-0 (sp) (sp + 3) (sp + 2), sp sp + 4 then skip unconditionally , , mbe, rbe (sp + 4) 0, 0, pc 13 , pc 12 (sp + 1) pc 11-0 (sp) (sp + 3) (sp + 2), sp sp + 6 then skip unconditionally reti note 1 3 mbe, rbe, pc 13, pc 12 (sp + 1) pc 11-0 (sp) (sp + 3) (sp + 2) psw (sp + 4) (sp + 5), sp sp + 6 0, 0 pc 13 , pc 12 (sp + 1) pc 11-0 (sp) (sp + 3) (sp + 2) psw (sp + 4) (sp + 5), sp sp + 6 note the shaded portion is supported only in the mkii mode. the others are supported in the mki mode. subroutine/ stack control
chapter 11 instruction set 352 user? manual u10201ej2v4um00 machine cycle instructions mnemonic operand bytes operation skip condition addressing area subroutine/ stack control interrupt control push rp 1 1 (sp ?1) (sp ?2) rp, sp sp ?2 bs 2 2 (sp ?1) mbs, (sp ?2) rbs, sp sp? pop rp 1 1 rp (sp + 1) (sp), sp sp + 2 bs 2 2 mbs (sp + 1), rbs (sp), sp sp + 2 ei 2 2 ime (ips.3) 1 ie 22ie 1 di 2 2 ime (ips.3) 0 ie 22ie 0 i/o in note2 a, port n 22a port n (n=0-8) xa, port n 2 2 xa port n+1 , port n (n=4, 6) out note2 port n , a 2 2 port n a (n=2-8) port n , xa 2 2 port n+1 , port n xa (n = 4, 6) cpu control halt 2 2 set halt mode (pcc.2 1) stop 2 2 set stop mode (pcc.3 1) nop 1 1 no operation special sel rbn 2 2 rbs n (n=0-3) mbn 2 2 mbs n (n=0-2, 15) geti note1, 3 taddr 1 3 . tbr instruction *10 pc 13-0 (taddr) 5-0 + (taddr+1) . tcall instruction (sp?) (sp?) (sp?) pc 11-0 (sp?) mbe, rbe, pc 13 , pc 12 pc 13-0 (taddr) 5-0 + (taddr+1) sp sp? . other than tbr and tcall instructions executes instruction of (taddr) (taddr+1) 13 . tbr instruction pc 13-0 (taddr) 5-0 + (taddr+1) 4 . tcall instruction (sp?)(sp?) (sp?) (sp?) 0, 0, pc 13-0 (sp?) , , mbe, rbe pc 13-0 (taddr) 5-0 + (taddr+1) sp sp-6 3 . other than tbr and tcall instructions executes instruction of (taddr) (taddr+1) notes 1. the shaded portion is supported only in the mkii mode. the others are supported in the mki mode. 2. to execute in/out instruction, it is necessary that mbe = 0 or mbe = 1, mbs = 15. 3. tbr and tcall instructions are the assembler directives for table definition. depends on referenced instruction depends on referenced instruction
chapter 11 instruction set 353 user? manual u10201ej2v4um00 11.3 op code of each instruction (1) description of symbol of op code i n : immediate data for n4 or n8 d n : immediate data for mem b n : immediate data for bit n n : immediate data for n or ie t n : immediate data for taddr 1/2 a n : immediate data for [relative address distance from branch destination address (2-16)] ?1 s n : immediate data for 1? complement of [relative address distance from branch destination address (15- 1)] r 2 r 1 r 0 reg 000a 001x 010l 011h 100e 101d 110c 111b reg reg1 p 2 p 1 p 0 reg-pair 000xa 001xa' 010hl 011hl' 100de 101de' 110bc 111bc' rp' rp'1 q 2 q 1 q 0 addressing 000@hl 0 1 0 @hl+ 0 1 1 @hl 100@de 101@dl p 2 p 1 reg-pair 00xa 01hl 10de 11bc rp2 rp1 rp n 5 n 2 n 1 n 0 ie 0000iebt 0010iew 0100iet0 0101i ecsi 0110ie0 0111ie2 1000ie4 1100iet1 1101iet2 1110ie1 @rpa @rpa1
chapter 11 instruction set 354 user? manual u10201ej2v4um00 (2) op code for bit manipulation addressing *1 in the operand field indicates the following three types: fmem.bit pmem.@l @h+mem.bit the second byte *2 of the op code corresponding to the above addressing is as follows: *1 2nd byte of op code accessible bit fmem. bit 1 0 b 1 b 0 f 3 f 2 f 1 f 0 bit of fb0h-fbfh that can be manipulated 11b 1 b 0 f 3 f 2 f 1 f 0 bit of ff0h-fffh that can be manipulated pmem. @l 0100g 3 g 2 g 1 g 0 bit of fc0h-fffh that can be manipulated @h+mem. bit 0 0 b 1 b 0 d 3 d 2 d 1 d 0 bit of accessible memory bank that can be manipulated b n : immediate data for bit f n : immediate data for fmem (indicates lower 4 bits of address) g n : immediate data for pmem (indicates bits 5-2 of address) d n : immediate data for mem (indicates lower 4 bits of address)
chapter 11 instruction set 355 user? manual u10201ej2v4um00 instruction mnemonic operand op code b 1 b 2 b 3 transfer mov a, #n4 0111i 3 i 2 i 1 i 0 reg1, #n4 10011010i 3 i 2 i 1 i 0 1r 2 r 1 r 0 rp, #n8 10001p 2 p 1 1i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 a, @rpa1 11100q 2 q 1 q 0 xa, @hl 1010101000011000 @hl, a 11101000 @hl, xa 1010101000010000 a, mem 10100011d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xa, mem 10100010d 7 d 6 d 5 d 4 d 3 d 2 d 1 0 mem, a 10010011d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 mem, xa 10010010d 7 d 6 d 5 d 4 d 3 d 2 d 1 0 a, reg 1001100101111r 2 r 1 r 0 xa, rp' 1010101001011p 2 p 1 p 0 reg1, a 1001100101110r 2 r 1 r 0 rp'1, xa 1010101001010p 2 p 1 p 0 xch a, @rpa1 11101q 2 q 1 q 0 xa, @hl 1010101000010001 a, mem 10110011d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xa, mem 10110010d 7 d 6 d 5 d 4 d 3 d 2 d 1 0 a, reg1 11011r 2 r 1 r 0 xa, rp' 1010101001000p 2 p 1 p 0 movt xa, @pcde 11010100 xa, @pcxa 11010000 xa, @bcxa 11010001 xa, @bcde 11010101 bit transfer mov1 cy, *1 10111101 *2 *1 , cy 10011011 *2 table reference
chapter 11 instruction set 356 user? manual u10201ej2v4um00 op code b 1 b 2 b 3 operation adds a, #n4 0110i 3 i 2 i 1 i 0 xa, #n8 10111001i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 a, @hl 11010010 xa, rp' 1010101011001p 2 p 1 p 0 rp'1, xa 1010101011000p 2 p 1 p 0 addc a, @hl 10101001 xa, rp' 1010101011011p 2 p 1 p 0 rp'1, xa 1010101011010p 2 p 1 p 0 subs a, @hl 10101000 xa, rp' 1010101011101p 2 p 1 p 0 rp'1, xa 1010101011100p 2 p 1 p 0 subc a, @hl 10111000 xa, rp' 1010101011111p 2 p 1 p 0 rp'1, xa 1010101011110p 2 p 1 p 0 and a, #n4 100110010011i 3 i 2 i 1 i 0 a, @hl 10010000 xa, rp' 1010101010011p 2 p 1 p 0 rp'1, xa 1010101010010p 2 p 1 p 0 or a, #n4 100110010100i 3 i 2 i 1 i 0 a, @hl 10100000 xa, rp' 1010101010101p 2 p 1 p 0 rp'1, xa 1010101010100p 2 p 1 p 0 xor a, #n4 100110010101i 3 i 2 i 1 i 0 a, @hl 10110000 xa, rp' 1010101010111p 2 p 1 p 0 rp'1, xa 1010101010110p 2 p 1 p 0 rorc a 10011000 not a 1001100101011111 instruction mnemonic operand accumulator manipula- tion
chapter 11 instruction set 357 user? manual u10201ej2v4um00 op code b 1 b 2 b 3 incs reg 11000r 2 r 1 r 0 rp1 10001p 2 p 1 0 @hl 1001100100000010 mem 10000010d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 decs reg 11001r 2 r 1 r 0 rp' 1010101001101p 2 p 1 p 0 comparison ske reg, #n4 10011010i 3 i 2 i 1 i 0 0r 2 r 1 r 0 @hl, #n4 100110010110i 3 i 2 i 1 i 0 a, @hl 10000000 xa, @hl 1010101000011001 a, reg 1001100100001r 2 r 1 r 0 xa, rp' 1010101001001p 2 p 1 p 0 set1 cy 11100111 clr1 cy 11100110 skt cy 11010111 not1 cy 11010110 set1 mem.bit 1 0 b 1 b 0 0101d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 *1 10011101 *2 clr1 mem.bit 1 0 b 1 b 0 0100d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 *1 10011100 *2 skt mem.bit 1 0 b 1 b 0 0111d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 *1 10111111 *2 skf mem.bit 1 0 b 1 b 0 0110d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 *1 10111110 *2 sktclr *1 10011111 *2 and1 cy, *1 10101100 *2 or1 cy, *1 10101110 *2 xor1 cy, *1 10111100 *2 instruction mnemonic operand increment/ decrement carry flag manipula- tion memory bit manipula- tion
chapter 11 instruction set 358 user? manual u10201ej2v4um00 op code b 1 b 2 b 3 branch br !addr 1010101100 addr $addr1 0000a 3 a 2 a 1 a 0 1111s 3 s 2 s 1 s 0 pcde 1001100100000100 pcxa 1001100100000000 bcde 1001100100000101 bcxa 1001100100000001 bra !addr1 101110100 addr1 brcb !caddr 0101 caddr calla !addr1 101110110 addr1 call !addr 1010101101 addr callf !faddr 01000 faddr ret 11101110 rets 11100000 reti 11101111 push rp 01001p 2 p 1 1 bs 1001100100000111 pop rp 01001p 2 p 1 0 bs 1001100100000110 ei 1001110110110010 ie 1001110110n 5 11n 2 n 1 n 0 di 1001110010110010 ie 1001110010n 5 11n 2 n 1 n 0 i/o in a, portn 101000111111n 3 n 2 n 1 n 0 xa, portn 101000101111n 3 n 2 n 1 n 0 out portn, a 100100111111n 3 n 2 n 1 n 0 portn, xa 100100101111n 3 n 2 n 1 n 0 cpu control halt 1001110110100011 stop 1001110110110011 nop 01100000 special sel rbn 10011001001000n 1 n 0 mbn 100110010001n 3 n 2 n 1 n 0 geti taddr 0 0 t 5 t 4 t 3 t 2 t 1 t 0 instruction mnemonic operand subroutine/ stack control (+16) (+2) (?) (?5) ~ ~ interrupt control
chapter 11 instruction set 359 user? manual u10201ej2v4um00 11.4 instruction function and application this section describes the functions and applications of the respective instructions. the instructions that can be used and the functions of the instructions differ between the mki and mkii modes of the pd753036, and 753p3036. read the descriptions on the following pages according to the following guidance: how to read : this instruction can be used commonly to all the following: pd753036 pd75p3036 : this instruction can be used only in the mki mode of the pd753036, and 753p3036. : this instruction can be used only in the mkii mode of the pd753036, and 75p3036. : this instruction can be used commonly in the mki and mkii modes of the pd753036, and 75p3036, but the function may differ between the mki and mkii modes. in the mki mode, refer to the description under the heading [mki mode]. in the mkii mode, read the description under the heading [mkii mode]. in mki and mkii modes i ii i/ii
chapter 11 instruction set 360 user? manual u10201ej2v4um00 11.4.1 transfer instructions mov a, #n4 function: a n4 n4 = i 3-0 : 0-fh transfers 4-bit immediate data n4 to the a register (4-bit accumulator). this instruction has a string effect (group a), and if this instruction is followed by mov a, #n4 or mov xa, #n8, the string-effect instruction following the instruction executed is treated as nop. application example (1) to set 0bh to the accumulator mov a, #0bh (2) to select data output to port 3 from 0 to 2 a0: mov a, #0 a1: mov a, #1 a2: mov a, #2 out port3, a mov reg1, #n4 function: reg1 n4 n4 = i 3-0 0-fh transfers 4-bit immediate data n4 to a register reg1 (x, h, l, d, e, b, or c). mov xa, #n8 function: xa n8 n8 = i 7-0 : 00h-ffh transfers 8-bit immediate data n8 to register pair xa. this instruction has a string effect, and if two or more of this instruction are executed in succession or if this instruction is followed by the mov a, #n4 instruction, the instruction following this instruction is treated as nop.
chapter 11 instruction set 361 user? manual u10201ej2v4um00 mov hl, #n8 function: hl n8 n8 = i 7-0 : 00h-ffh transfers 8-bit immediate data n8 to register pair hl. this instruction has a string effect. if two or more of this instructions are executed in succession, those that follow the first instruction are treated as nop. mov rp2, #n8 function: rp2 n8 n8 = i 7-0 : 00h-ffh transfers 8-bit immediate data n8 to register pair rp2 (bc, de). mov a, @hl function: a (hl) transfers the contents of the data memory addressed by register pair hl to the a register. mov a, @hl+ function: a (hl), l l + 1 skip if l = 0h transfers the contents of the data memory addressed by register pair hl to the a register. after that, automatically increments the contents of the l register by one. when the value of the l register reaches 0h as a result, skips the next one instruction. mov a, @hl function: a (hl), l l ?1 skip if l = fh transfers the contents of the data memory addressed by register pair hl to the a register. after that, automatically decrements the contents of the l register by one. when the value of the l register reaches fh as a result, skips the next one instruction.
chapter 11 instruction set 362 user? manual u10201ej2v4um00 mov a, @rpa1 function: a (rpa) where rpa = hl+: skip if l = 0 where rpa = hl? skip if l = fh transfers the contents of the data memory addressed by register pair rpa (hl, hl+, hl? de, or dl) to the a register. if autoincrement (hl+) is specified as rpa, the contents of the l register are automatically incremented by one after the data has been transferred. if the contents of the l register become 0 as a result, the next one instruction is skipped. if autodecrement (hl? is specified as rpa, the contents of the l register are automatically decremented by one after the data has been transferred. if the contents of the l register become fh as a result, the next one instruction is skipped. mov xa, @hl function: a (hl), x (hl+1) transfers the contents of the data memory addressed by register pair hl to the a register, and the contents of the next memory address to the x register. if the contents of the l register are a odd number, an address whose least significant bit is ignored is transferred. application example to transfer the data at addresses 3eh and 3fh to register pair xa mov hl, #3eh mov xa, @hl mov @hl, a function: (hl) a transfers the contents of the a register to the data memory addressed by register pair hl. mov @hl, xa function: (hl) a, (hl+1) x transfers the contents of the a register to the data memory addressed by register pair hl, and the contents of the x register to the next memory address. however, if the contents of the l register are a odd number, an address whose least significant bit is ignored is transferred.
chapter 11 instruction set 363 user? manual u10201ej2v4um00 mov a, mem function: a (mem) mem = d 7-0 : 00h-ffh transfers the contents of the data memory addressed by 8-bit immediate data mem to the a register. mov xa, mem function: a (mem), x (mem+1) mem = d 7-0 : 00h-feh transfers the contents of the data memory addressed by 8-bit immediate data mem to the a register and the contents of the next address to the x register. the address that can be specified by mem is an even address. application example to transfer the data at addresses 40h and 41h to register pair xa mov xa, 40h mov mem, a function: (mem) a mem = d 7-0 : 00h-ffh transfers the contents of the a register to the data memory addressed by 8-bit immediate data mem. mov mem, xa function: (mem) a, (mem+1) x mem = d 7-0 : 00h-feh transfers the contents of the a register to the data memory addressed by 8-bit immediate data mem and the contents of the x register to the next memory address. the address that can be specified by mem is an even address. mov a, reg function: a reg transfers the contents of register reg (x, a, h, l, d, e, b, or c) to the a register.
chapter 11 instruction set 364 user? manual u10201ej2v4um00 mov xa, rp function: xa rp transfers the contents of register pair rp?(xa, hl, de, bc, xa? hl? de? or bc? to register pair xa. application example to transfer the data of register pair xa?to register pair xa mov xa, xa mov reg1, a function: reg1 a transfers the contents of the a register to register reg1 (x, h, l, d, e, b, or c). mov rp?, xa function: rp? xa transfers the contents of register pair xa to register pair rp? (hl, de, bc, xa? hl? de? or bc?.
chapter 11 instruction set 365 user? manual u10201ej2v4um00 xch a, @hl function: a ? (hl) exchanges the contents of the a register with the contents of the data memory addressed by register pair hl. xch a, @hl+ function: a ? (hl), l l + 1 skip if l = 0h exchanges the contents of the a register with the contents of the data memory addressed by register pair hl. after that, automatically increments the contents of the l register by one. if the contents of the l register reaches 0h as a result, skips the next one instruction. xch a, @hl function: a ? (hl), l l ?1 skip if l = fh exchanges the contents of the a register with the contents of the data memory addressed by register pair hl. after that, automatically decrements the contents of the l register by one. if the contents of the l register reaches fh as a result, skips the next one instruction. xch a, @rpa1 function: a ? (rpa) where rpa = hl+: skip if l = 0 where rpa = hl? skip if l = fh exchanges the contents of the a register with the contents of the data memory addressed by register pair rpa (hl, hl+, hl? de, or dl). if autoincrement (hl+) or autodecrement (hl? is specified as rpa, the contents of the l register are automatically incremented or decremented by one after the data have been exchanged. if the result is 0 in the case of hl+ and fh in the case of hl? the next one instruction is skipped. application example to exchange the data at data memory addresses 20h through 2fh with the data at addresses 30h through 3fh sel mb0 mov d, #2 mov hl, #30h loop: xch a, @hl ; a (3 ) xch a, @dl ; a (2 ) xch a, @hl+ ; a (3 ) br loop
chapter 11 instruction set 366 user? manual u10201ej2v4um00 xch xa, @hl function: a ? (hl), x ? (hl+1) exchanges the contents of the a register with the contents of the data memory addressed by register pair hl, and the contents of the x register with the contents of the next address. if the contents of the l register are an odd number, however, an address whose least significant bit is ignored is specified. xch a, mem function: a ? (mem) mem = d 7-0 : 00h-feh exchanges the contents of the a register with the contents of the data memory addressed by 8-bit immediate data mem. xch xa, mem function: a ? (mem), x ? (mem+1) mem = d 7-0 : 00h-feh exchanges the contents of the a register with the data memory contents addressed by 8-bit immediate data mem, and the contents of the x register with the contents of the next memory address. the address that can be specified by mem is an even address. xch a, reg1 function: a ? reg1 exchanges the contents of the a register with the contents of register reg1 (x, h, l, d, e, b, or c). xch xa, rp function: xa ? rp exchanges the contents of register pair xa with the contents of register pair rp?(xa, hl, de, bc, xa? hl? de? or bc?.
chapter 11 instruction set 367 user? manual u10201ej2v4um00 11.4.2 table reference instruction movt xa, @pcde function: xa rom (pc 13-8 +de) transfers the lower 4 bits of the table data in the program memory addressed when the lower 8 bits (pc 7-0 ) of the program counter (pc) are replaced with the contents of register pair de, to the a register, and the higher 4 bits to the x register. the table address is determined by the contents of the program counter (pc) when this instruction is executed. the necessary data must be programmed to the table area in advance by using an assembler directive (db instruction). the program counter is not affected by execution of this instruction. this instruction is useful for successively referencing table data. example pc 13 _ 8 13 8 d 3 _ 0 74 e 3 _ 0 30 x 30 a 30 table data h 74 table data l 30 table address program memory
chapter 11 instruction set 368 user s manual u10201ej2v4um00 caution the movt xa, @pcde instruction usually references the table data in page where the instruction exists. if the instruction is at address ffh, however, not the table data in the page where the instruction exists, but the table data in the next page is referenced. 70 02ffh 0300h page 3 page 2 program memory a for example, if the movt xa, @pcde instruction is located at position a in the above figure, the table data in page 3, not page 2, specified by the contents of register pair de is transferred to register pair xa. application example to transfer the 16-byte data at program memory addresses f0h through ffh to data memory addresses 30h through 4fh sub: sel mb0 mov hl, #30h ; hl 30h mov de, #0f0h ; de f0h loop: movt xa, @pcde ; xa table data mov @hl, xa ; (hl) xa incs hl ; hl hl+2 incs hl incs e ; e e+1 br loop ret org f0h db h, h, ... ; table data
chapter 11 instruction set 369 user s manual u10201ej2v4um00 movt xa, @pcxa function: xa rom (pc 13-8 +xa) transfers the lower 4 bits of the table data in the program memory addressed when the lower 8 bits (pc 7-0 ) of the program counter (pc) are replaced with the contents of register pair xa, to the a register, and the higher 4 bits to the x register. the table address is determined by the contents of the pc when this instruction is executed. the necessary data must be programmed to the table area in advance by using an assembler directive (db instruction). the pc is not affected by execution of this instruction. caution if an instruction exists at address ffh, the table data of the next page is transferred, in the same manner as movt xa, @pcde. movt xa, @bcde function: xa rom (b 1, 0 +cde) transfers the lower 4 bits of the table data (8-bit) in the program memory addressed by the lower 3 bits of register b and the contents of registers c, d, and e, to the a register, and the higher 4 bits to the x register. the necessary data must be programmed to the table area in advance by using an assembler directive (db instruction). the pc is not affected by execution of this instruction. example b 1, 0 cde 13 1211 87 43 0 table data h x 30 table data l a 30
chapter 11 instruction set 370 user s manual u10201ej2v4um00 movt xa, @bcxa function: xa rom (b 1, 0 +cxa) transfers the lower 4 bits of the table data (8-bit) in the program memory addressed by the lower 3 bits of register b and the contents of registers c, x, and a, to the a register, and the higher 4 bits to the x register. the necessary data must be programmed to the table area in advance by using an assembler directive (db instruction). the pc is not affected by execution of this instruction. example b 1, 0 cxa 13 1211 87 43 0 table data h x 30 table data l a 30
chapter 11 instruction set 371 user s manual u10201ej2v4um00 11.4.3 bit transfer instruction mov1 cy, fmem.bit mov1 cy, pmem.@l mov1 cy, @h+mem.bit function: cy (bit specified by operand) transfers the contents of the data memory addressed in the bit manipulating addressing mode (fmem.bit, pmem.@l, or @h+mem.bit) to the carry flag (cy). mov1 fmem.bit, cy mov1 pmem.@l, cy mov1 @h+mem.bit, cy function: (bit specified by operand) cy transfers the contents of the carry flag (cy) to the data memory bit addressed in the bit manipulation addressing mode (fmem.bit, pmem.@l, or @h+mem.bit). application example to output the flag of bit 3 at data memory address 3fh to the bit 2 of port 3 flag equ 3fh.3 sel mb0 mov h, #flag shr6 ; h higher 4 bits of flag mov1 cy, @h+flag ; cy flag mov1 port3.2, cy ; p32 cy
chapter 11 instruction set 372 user? manual u10201ej2v4um00 11.4.4 operation instruction adds a, #n4 function: a a+n4; skip if carry. n4 = l 3-0 : 0-fh adds 4-bit immediate data n4 to the contents of the a register. if a carry occurs as a result, the next one instruction is skipped. the carry flag is not affected. if this instruction is used in combination with addc a, @hl or subc a, @hl instruction, it can be used as a base number adjustment instruction (refer to 11.1.4 base number adjustment instruction ). adds xa, #n8 function: xa xa+n8; skip if carry. n8 = i 7-0 : 00h-ffh adds 8-bit immediate data n8 to the contents of register pair xa. if a carry occurs as a result, the next one instruction is skipped. the carry flag is not affected. adds a, @hl function: a a + (hl); skip if carry. adds the contents of the data memory addressed by register pair hl to the contents of the a register. if a carry occurs as a result, the next one instruction is skipped. the carry flag is not affected. adds xa, rp function: xa xa + rp? skip if carry. adds the contents of register pair rp?(xa, hl, de, bc, xa? hl? de? or bc? to the contents of register pair xa. if a carry occurs as a result, the next one instruction is skipped. the carry flag is not affected. adds rp?, xa function: rp? rp? + xa; skip if carry. adds the contents of register pair xa to register pair rp? (hl, de, bc, xa? hl? de? or bc?. if a carry occurs as a result, the next one instruction is skipped. the carry flag is not affected. application example to shift a register pair to the left mov xa, rp? adds rp?, xa nop
chapter 11 instruction set 373 user? manual u10201ej2v4um00 addc a, @hl function: a, cy a+ (hl) +cy adds the contents of the data memory addressed by register pair hl to the contents of the a register, including the carry flag. if a carry occurs as a result, the carry flag is set; if not, the carry flag is reset. if the adds a, #n4 instruction is placed next to this instruction, and if a carry occurs as a result of executing this instruction, the adds a, #n4 instruction is skipped. if a carry does not occur, the adds a, #n4 instruction is executed, and a function that disables the skip function of the adds a, #n4 instruction is effected. therefore, these instructions can be used in combination for base number adjustment (refer to 11.1.4 base number adjustment instruction ). addc xa, rp function: xa, cy xa + rp?+ cy adds the contents of register pair rp?(xa, hl, de, bc, xa? hl? de? or bc? to the contents of register pair xa, including the carry. if a carry occurs as a result, the carry flag is set; if not, the carry flag is reset. addc rp?, xa function: rp?, cy rp?+xa+cy adds the contents of register pair xa to the contents of register pair rp? (hl, de, bc, xa? hl? de? or bc?, including the carry flag. if a carry occurs as a result, the carry flag is set; if not, the carry flag is reset.
chapter 11 instruction set 374 user? manual u10201ej2v4um00 subs a, @hl function: a a ?(hl); skip if borrow. subtracts the contents of the data memory addressed by register pair hl from the contents of the a register, and sets the result to the a register. if a borrow occurs as a result, the next one instruction is skipped. the carry flag is not affected. subs xa, rp function: xa xa ?rp? skip if borrow. subtracts the contents of register pair rp?(xa, hl, de, bc, xa? hl? de? or bc? from the contents of register pair xa, and sets the result to register pair xa. if a borrow occurs as a result, the next one instruction is skipped. the carry flag is not affected. application example to compare specified data memory contents with the contents of a register pair mov xa, mem subs xa, rp ; (mem) rp ; (mem) < rp subs rp?, xa function: rp? rp? ?xa; skip if borrow. subtracts the contents of register pair xa from register pair rp? (hl, de, bc, xa? hl? de? or bc?, and sets the result to specified register pair rp?. if a borrow occurs as a result, the next one instruction is skipped. the carry flag is not affected.
chapter 11 instruction set 375 user? manual u10201ej2v4um00 subc a, @hl function: a, cy a ?(hl) ?cy subtracts the contents of the data memory addressed by register pair hl to the contents from the a register, including the carry flag, and sets the result to the a register. if a borrow occurs as a result, the carry flag is set; if not, the carry flag is reset. if the adds a, #n4 instruction is placed next to this instruction, and if a borrow does not occur as a result of executing this instruction, the adds a, #n4 instruction is skipped. if a borrow occurs, the adds a, #n4 instruction is executed, and a function that disables the skip function of the adds a, #n4 instruction is effected. therefore, these instructions can be used in combination for base number adjustment (refer to 11.1.4 base number adjustment instruction ). subc xa, rp function: xa, cy xa ?rp??cy subtracts the contents of register pair rp?(xa, hl, de, bc, xa? hl? de? or bc? from the contents of register pair xa, including the carry, and sets the result to register pair xa. if a borrow occurs as a result, the carry flag is set; if not, the carry flag is reset. subc rp?, xa function: rp?, cy rp? ?xa ?cy subtracts the contents of register pair xa from the contents of register pair rp? (hl, de, bc, xa? hl? de? or bc?, including the carry flag, and sets the result to specified register pair rp?. if a borrow occurs as a result, the carry flag is set; if not, the carry flag is reset.
chapter 11 instruction set 376 user? manual u10201ej2v4um00 and a, #n4 function: a a n4 n4 = l 3-0 : 0-fh ands 4-bit immediate data n4 with the contents of the a register, and sets the result to the a register. application example to clear the higher 2 bits of the accumulator to 0 and a, #0011b and a, @hl function: a a (hl) ands the contents of the data memory addressed by register pair hl with the contents of the a register, and sets the result to the a register. and xa, rp function: xa xa rp ands the contents of register pair rp?(xa, hl, de, bc, xa? hl? de? or bc? with the contents of register pair xa, and sets the result to register pair xa. and rp?, xa function: rp? rp? xa ands the contents of register pair xa with register pair rp? (hl, de, bc, xa? hl? de? or bc?, and sets the result to a specified register pair.
chapter 11 instruction set 377 user? manual u10201ej2v4um00 or a, #n4 function: a a n4 n4 = l 3-0 : 0-fh ors 4-bit immediate data n4 with the contents of the a register, and sets the result to the a register. application example to set the lower 3 bits of the accumulator to 1 or a, #0111b or a, @hl function: a a (hl) ors the contents of the data memory addressed by register pair hl with the contents of the a register, and sets the result to the a register. or xa, rp function: xa xa rp ors the contents of register pair rp?(xa, hl, de, bc, xa? hl? de? or bc? with the contents of register pair xa, and sets the result to register pair xa. or rp?, xa function: rp? rp? xa ors the contents of register pair xa with register pair rp? (hl, de, bc, xa? hl? de? or bc?, and sets the result to a specified register pair.
chapter 11 instruction set 378 user? manual u10201ej2v4um00 xor a, #n4 function: a a n4 n4 = l 3-0 : 0-fh exclusive-ors 4-bit immediate data n4 with the contents of the a register, and sets the result to the a register. application example to invert the higher 4 bits of the accumulator xor a, #1000b xor a, @hl function: a a (hl) exclusive-ors the contents of the data memory addressed by register pair hl with the contents of the a register, and sets the result to the a register. xor xa, rp function: xa xa rp exclusive-ors the contents of register pair rp?(xa, hl, de, bc, xa? hl? de? or bc? with the contents of register pair xa, and sets the result to register pair xa. xor rp?, xa function: rp? rp? xa exclusive-ors the contents of register pair xa with register pair rp? (hl, de, bc, xa? hl? de? or bc?, and sets the result to a specified register pair.
chapter 11 instruction set 379 user? manual u10201ej2v4um00 11.4.5 accumulator manipulation instruction rorc a function: cy a 0 , a n-1 a n , a 3 cy (n = 1-3) rotates the contents of the a register (4-bit accumulator) 1 bit to the left with the carry flag. not a function: a a takes 1? complement of the a register (4-bit accumulator) (inverts the bits of the accumulator). 0 cy 0 3 1 2 0 1 1 0 a before execution 1 0010 after execution rorc a . . . .
chapter 11 instruction set 380 user s manual u10201ej2v4um00 11.4.6 increment/decrement instruction incs reg function: reg reg+1; skip if reg = 0 increments the contents of register reg (x, a, h, l, d, e, b, or c). if reg = 0 as a result, the next one instruction is skipped. incs rp1 function: rp1 rp1+1; skip if rp1 = 00h increments the contents of register pair rp1 (hl, de, or bc). if rp1 = 00h as a result, the next one instruction is skipped. incs @hl function: (hl) (hl)+1; skip if (hl) = 0 increments the contents of the data memory addressed by pair register hl. if the contents of the data memory become 0 as a result, the next one instruction is skipped. incs mem function: (mem) (mem) + 1; skip if (mem) = 0, mem = d 7-0 : 00h-ffh increments the contents of the data memory addressed by 8-bit immediate data mem. if the contents of the data memory become 0 as a result, the next one instruction is skipped. decs reg function: reg reg 1; skip if reg = fh decrements the contents of register reg (x, a, h, l, d, e, b, or c). if reg = fh as a result, the next one instruction is skipped. decs rp function: rp rp 1; skip if rp = ffh decrements the contents of register pair rp' (xa, hl, de, bc, xa', hl', de', or bc'). if rp = ffh as a result, the next one instruction is skipped.
chapter 11 instruction set 381 user s manual u10201ej2v4um00 11.4.7 compare instruction ske reg, #n4 function: skip if reg = n4 n4 = i 3-0 : 0-fh skips the next one instruction if the contents of register reg (x, a, h, l, d, e, b, or c) are equal to 4-bit immediate data n4. ske @hl, #n4 function: skip if (hl) = n4 n4 = i 3-0 : 0-fh skips the next one instruction if the contents of the data memory addressed by register pair hl are equal to 4- bit immediate data n4. ske a, @hl function: skip if a = (hl) skips the next one instruction if the contents of the a register are equal to the contents of the data memory addressed by register pair hl. ske xa, @hl function: skip if a = (hl) and x = (hl + 1) skips the next one instruction if the contents of the a register are equal to the contents of the data memory addressed by register pair hl and if the contents of the x register are equal to the contents of the next memory address. however, if the contents of the l register are an odd number, an address whose least significant address is ignored is specified. ske a, reg function: skip if a = reg skips the next one instruction if the contents of the a register are equal to register reg (x, a, h, l, d, e, b, or c). ske xa, rp function: skip if xa = rp skips the next one instruction if the contents of register pair xa are equal to the contents of register pair rp (xa, hl, de, bc, xa , hl , de , or bc ).
chapter 11 instruction set 382 user s manual u10201ej2v4um00 11.4.8 carry flag manipulation instruction set1 cy function: cy 1 sets the carry flag. clr1 cy function: cy 0 clears the carry flag. skt cy function: skip if cy = 1 skips the next one instruction if the carry flag is 1. not1 cy function: cy cy inverts the carry flag. therefore, sets the carry flag to 1 if it is 0, and clears the flag to 0 if it is 1.
chapter 11 instruction set 383 user s manual u10201ej2v4um00 11.4.9 memory bit manipulation instruction set1 mem.bit function: (mem.bit) 1 mem = d 7-0 : 00h-ffh, bit = b 1-0 : 0-3 sets the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate data mem. set1 fmem.bit set1 pmem.@l set1 @h+mem.bit function: (bit specified by operand) 1 sets the bit of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@l, or @h+mem.bit). clr1 mem.bit function: (mem.bit) 0 mem = d 7-0 : 00h-ffh, bit = b 1-0 : 0-3 clears the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate data mem. clr1 fmem.bit clr1 pmem.@l clr1 @h+mem.bit function: (bit specified by operand) 0 clears the bit of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@l, or @h+mem.bit).
chapter 11 instruction set 384 user s manual u10201ej2v4um00 skt mem.bit function: skip if (mem.bit) = 1 mem = d 7-0 : 00h-ffh, bit = b 1-0 : 0-3 skips the next one instruction if the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate data mem is 1. skt fmem.bit skt pmem.@l skt @h+mem.bit function: skip if (bit specified by operand) = 1 skips the next one instruction if the bit of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@l, or @h+mem.bit) is 1. skf mem.bit function: skip if (mem.bit) = 0 mem = d 7-0 : 00h-ffh, bit = b 1-0 : 0-3 skips the next one instruction if the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate data mem is 0. skf fmem.bit skf pmem.@l skf @h+mem.bit function: skip if (bit specified by operand) = 0 skips the next one instruction if the bit of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@l, or @h+mem.bit) is 0.
chapter 11 instruction set 385 user s manual u10201ej2v4um00 sktclr fmem.bit sktclr pmem.@l sktclr @h+mem.bit function: skip if (bit specified by operand) = 1 then clear skips the next one instruction if the bit of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@l, or @h+mem.bit) is 1, and clears the bit to 0 . and1 cy, fmem.bit and1 cy, pmem.@l and1 cy, @h+mem.bit function: cy cy (bit specified by operand) ands the content of the carry flag with the contents of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@l, or @h+mem.bit), and sets the result to the carry flag. or1 cy, fmem.bit or1 cy, pmem.@l or1 cy, @h+mem.bit function: cy cy (bit specified by operand) ors the content of the carry flag with the contents of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@l, or @h+mem.bit), and sets the result to the carry flag. xor1 cy, fmem.bit xor1 cy, pmem.@l xor1 cy, @h+mem.bit function: cy cy (bit specified by operand) exclusive-ors the content of the carry flag with the contents of the data memory addressed in the bit manipulation addressing mode (fmem.bit, pmem.@l, or @h+mem.bit), and sets the result to the carry flag.
chapter 11 instruction set 386 user s manual u10201ej2v4um00 11.4.10 branch instruction br addr function: pc 13-0 addr addr = 0000h-3fffh branches to an address specified by immediate data addr. this instruction is an assembler directive and is replaced by the assembler at assembly time with the optimum instruction from the br !addr, brcb !caddr, and br $addr instructions. br addr1 function: pc 13-0 addr1 addr1 = 0000h-3fffh branches to an address specified by immediate data addr1. this instruction is an assembler directive and is replaced by the assembler at assembly time with the optimum instruction from the bra !addr1, br !addr, brcb !caddr, and br $addr instructions. bra !addr1 function: pc 13-0 addr1 br !addr function: pc 13-0 addr addr = 0000h-3fffh transfers immediate data addr to the program counter (pc) and branches to an address specified by the pc. br $addr function: pc 13-0 addr addr = (pc 15) to (pc 1), (pc+2) to (pc+16) this is a relative branch instruction that has a branch range of ( 15 to 1) and (+2 to +16) from the current address. it is not affected by a page boundary or block boundary. ii ii
chapter 11 instruction set 387 user s manual u10201ej2v4um00 br $addr1 function: pc 13-0 addr1 addr1 = (pc 15) to (pc 1), (pc+2) to (pc+16) this is a relative branch instruction that has a branch range of ( 15 to 1) and (+2 to +16) from the current address. it is not affected by a page boundary or block boundary. brcb !caddr function: pc 13-0 pc 13,12 + caddr 11-0 caddr = n000h-nfffh n = pc 13,12 = 0-3 branches to an address specified by the lower 12 bits of the program counter (pc 11-0 ) replaced with 12-bit immediate data caddr. caution the brcb !caddr instruction usually branches execution in a block where the instruction exists. if the first byte of this instruction is at address 0ffeh or 0fffh, however, execution does not branch to block 0 but to block 1. ii i/ii 70 0fffh 1000h block 1 block 0 program memory 0ffeh a b if the brcb !caddr instruction is at position b in the figure above, execution branches to block 1, not block 0.
chapter 11 instruction set 388 user s manual u10201ej2v4um00 br pcde function: pc 13-0 pc 13-8 + de pc 7-4 d, pc 3-0 e branches to an address specified by the lower 8 bits of the program counter (pc 7-0 ) replaced with the contents of register pair de. the higher bits of the program counter are not affected. caution the br pcde instruction usually branches execution to the page where the instruction exists. if the first byte of the op code is at address fe or ffh, however, execution does not branch in that page, but to the next page. 70 02ffh 0300h page 3 page 2 program memory 02feh a b for example, if the br pcde instruction is at position a or b in the above figure, execution branches to the lower 8-bit address specified by the contents of register pair de in page 3, not in page 2. br pcxa function: pc 13-0 pc 13-8 + xa pc 7-4 x, pc 3-0 a branches to an address specified by the lower 8 bits of the program counter (pc 7-0 ) replaced with the contents of register pair xa. the higher bits of the program counter are not affected. caution this instruction branches execution to the next page, not to the same page, if the first byte of the op code is at address feh or ffh, in the same manner as the br pcde instruction.
chapter 11 instruction set 389 user s manual u10201ej2v4um00 br bcde function: pc 13-0 b 1,0 + cde example to branch to an address specified by the contents of the program counter replaced by the contents of registers b 1, 0 , c, d, and e br bcxa function: pc 13-0 b 1,0 + cxa example to branch to an address specified by the contents of the program counter replaced by the contents of registers b 1, 0 , c, x, and a i/ii tbr addr function: this is an assembler directive for table definition by the geti instruction. it is used to replace a 3-byte br !addr instruction with a 1-byte geti instruction. describe 12-bit address data as addr. for details, refer to ra75x assembler package user? manual - language (eeu-1363) . 13 12 11 10 b pc 8 30 c 74 30 d 30 30 e 13 12 11 10 b pc 8 30 c 74 30 x 30 30 a
chapter 11 instruction set 390 user s manual u10201ej2v4um00 11.4.11 subroutine/stack control instruction calla !addr1 function: (sp 2) , , mbe, rbe, (sp 3) pc 7-4 (sp 4) pc 3-0 , (sp 5) 0, 0, pc 13, pc 12 (sp 6) pc 11-8 pc 13-0 addr1, sp sp 6 call !addr function: [mki mode] (sp 1) pc 7-4 , (sp 2) pc 3-0 (sp 3) mbe, rbe, pc 13 , pc 12 (sp 4) pc 11-8 , pc 13-0 addr, sp sp 4 addr = 0000h-3fffh [mkii mode] (sp 2) , , mbe, rbe (sp 3) pc 7-4 , (sp 4) pc 3-0 (sp 5) 0, 0, pc 13 , pc 12 , (sp 6) pc 11-8 pc 13-0 addr, sp sp 6 saves the contents of the program counter (return address), mbe, and rbe to the data memory (stack) addressed by the stack pointer (sp), decrements the sp, and then branches to an address specified by 14-bit immediate data addr. i/ii ii
chapter 11 instruction set 391 user s manual u10201ej2v4um00 callf !faddr function: [mki mode] (sp 1) pc 7-4 , (sp 2) pc 3-0 (sp 3) mbe, rbe, pc 13 , pc 12 (sp 4) pc 11-8 , sp sp 4 pc 13-0 000+faddr faddr = 0000h-07ffh [mkii mode] (sp 2) , , mbe, rbe (sp 3) pc 7-4 , (sp 4) pc 3-0 (sp 5) 0, 0, pc 13 , pc 12 , (sp 6) pc 11-8 sp sp 6 pc 13-0 000+faddr faddr = 0000h-07ffh saves the contents of the program counter (return address), mbe, and rbe to the data memory (stack) addressed by the stack pointer (sp), decrements the sp, and then branches to an address specified by 11-bit immediate data faddr. the address range from which a subroutine can be called is limited to 0000h to 07ffh (0 to 2047). tcall !addr function this is an assembler directive for table definition by the geti instruction. it is used to replace a 3-byte call !addr instruction with a 1-byte geti instruction. describe 12-bit address data as addr. for details, refer to ra75x assembler package user? manual - language (eeu-1363) . i/ii
chapter 11 instruction set 392 user s manual u10201ej2v4um00 ret function: [mki mode] pc 11-8 (sp), mbe, rbe, pc 13 , pc 12 (sp+1) pc 3-0 (sp+2) pc 7-4 (sp+3), sp sp+4 [mkii mode] pc 11-8 (sp), 0, 0, pc 13 , pc 12 (sp+1) pc 3-0 (sp+2), pc 7-4 (sp+3) , , mbe, rbe (sp+4), sp sp+6 restores the contents of the data memory (stack) addressed by the stack pointer (sp) to the program counter (pc), memory bank enable flag (mbe), and register bank enable flag (rbe), and then increments the contents of the sp. caution all the flags of the program status word (psw) other than mbe and rbe are not restored. rets function: [mki mode] pc 11-8 (sp), mbe, rbe, pc 13 , pc 12 (sp+1) pc 3-0 (sp+2), pc 7-4 (sp+3), sp sp+4 then skip unconditionally [mkii mode] pc 11-8 (sp), 0, 0, pc 13 , pc 12 (sp+1) pc 3-0 (sp+2), pc 7-4 (sp+3) , , mbe, rbe (sp+4), sp sp+6 then skip unconditionally restores the contents of the data memory (stack) addressed by the stack pointer (sp) to the program counter (pc), memory bank enable flag (mbe), and register bank enable flag (rbe), increments the contents of the sp, and then skips unconditionally. caution all the flags of the program status word (psw) other than mbe and rbe are not restored. i/ii i/ii
chapter 11 instruction set 393 user s manual u10201ej2v4um00 reti function: [mki mode] pc 11-8 (sp), mbe, rbe, pc 13 , pc 12 (sp+1) pc 3-0 (sp+2), pc 7-4 (sp+3) psw l (sp+4), psw h (sp+5) sp sp+6 [mkii mode] pc 11-8 (sp), 0, 0, pc 13 , pc 12 (sp+1) pc 3-0 (sp+2), pc 7-4 (sp+3) psw l (sp+4), psw h (sp+5) sp sp+6 restores the contents of the data memory (stack) addressed by the stack pointer (sp) to the program counter (pc) and program status word (psw), and then increments the contents of the sp. this instruction is used to return execution from an interrupt service routine. i/ii
chapter 11 instruction set 394 user s manual u10201ej2v4um00 push rp function: (sp 1) rp h , (sp 2) rp l , sp sp 2 saves the contents of register pair rp (xa, hl, de, or bc) to the data memory (stack) addressed by the stack pointer (sp), and then decrements the contents of the sp. the higher 4 bits of the register pair (rp h , x, h, d, or b) are saved to the stack addressed by (sp 1), and the lower 4 bits (rp l : a, l, e, or c) are saved to the stack addressed by (sp 2). push bs function: (sp 1) mbs, (sp 2) rbs, sp sp 2 saves the contents of the memory bank select register (mbs) and register bank select register (rbs) to the data memory (stack) addressed by the stack pointer (sp), and then decrements the contents of the sp. pop rp function: rp l (sp), rp h (sp+1), sp sp+2 restores the contents of the data memory addressed by the stack pointer (sp) to register pair rp (xa, hl, de, or bc), and then decrements the contents of the stack pointer. the contents of (sp) are restored to the higher 4 bits of the register pair (rp h , x, h, d, or b), and the contents of (sp+1) are restored to the lower 4 bits (rp l : a, l, e, or c). pop bs function: rbs (sp), mbs (sp+1), sp sp+2 restores the contents of the data memory (stack) addressed by the stack pointer (sp) to the register bank select register (rbs) and memory bank select register (mbs), and then increments the contents of the sp.
chapter 11 instruction set 395 user s manual u10201ej2v4um00 11.4.12 interrupt control instruction ei function: ime (ips.3) 1 sets the interrupt mask enable flag (bit 3 of the interrupt priority select register) to 1 to enable interrupts. acknowledging an interrupt is controlled by an interrupt enable flag corresponding to the interrupt. ei ie function: ie 1 = n 5 , n 2-0 sets a specified interrupt enable flag (ie ) to 1 to enable acknowledging the corresponding interrupt ( = bt, csi, t0, t1, t2, w, 0, 1, 2, or 4). di function: ime (ips.3) 0 resets the interrupt mask enable flag (bit 3 of the interrupt priority select register) to 0 to disable all interrupts, regardless of the contents of the respective interrupt enable flags. di ie function: ie 1 = n 5 , n 2-0 resets a specified interrupt enable flag (ie ) to 0 to disable acknowledging the corresponding interrupt ( = bt, csi, t0, t1, t2, w, 0, 1, 2, or 4).
chapter 11 instruction set 396 user s manual u10201ej2v4um00 11.4.13 input/output instruction in a, portn function: a portn n = n 3-0 : 0-8 transfers the contents of a port specified by portn (n = 0-8) to the a register. caution when this instruction is executed, it is necessary that mbe = 0 or (mbe = 1, mbs = 15). n can be 0 to 8. the data of the output latch is loaded to the a register in the output mode, and the data of the port pins are loaded to the register in the input mode. in xa, portn function: a portn, x portn+1 n = n 3-0 : 4, 6 transfers the contents of the port specified by portn (n = 4 or 6) to the a register, and transfers the contents of the next port to the x register. caution only 4 or 6 can be specified as n. when this instruction is executed, it is necessary that mbe = 0 or (mbe = 1, mbs = 15). the data of the output latch is loaded to the a and x registers in the output mode, and the data of the port pins are loaded to the registers in the input mode. out portn, a function: portn a n = n 3-0 : 2-8 transfers the contents of the a register to the output latch of a port specified by portn (n = 2-8). caution when this instruction is executed, it is necessary that mbe = 0 or (mbe = 1, mbs = 15). only 2 to 8 can be specified as n. out portn, xa function: portn a, portn+1 x n = n 3-0 : 4, 6 transfers the contents of the a register to the output latch of a port specified by portn (n = 4 or 6), and the contents of the x register to the output latch of the next port. caution when this instruction is executed, it is necessary that mbe = 0 or (mbe = 1, mbs = 15). only 4 or 6 can be specified as n.
chapter 11 instruction set 397 user s manual u10201ej2v4um00 11.4.14 cpu control instruction halt function: pcc.2 1 sets the halt mode (this instruction sets the bit 2 of the processor clock control register). caution make sure that an nop instruction follows the halt instruction. stop function: pcc.3 1 sets the stop mode (this instruction sets the bit 3 of the processor clock control register). caution make sure that an nop instruction follows the stop instruction. nop function: executes nothing but consumes 1 machine cycle.
chapter 11 instruction set 398 user s manual u10201ej2v4um00 11.4.15 special instruction sel rbn function: rbs n n = n 1-0 : 0-3 sets 2-bit immediate data n to the register bank select register (rbs). sel mbn function: mbs n n = n 3-0 : 0-2, 15 transfers 4-bit immediate data n to the memory bank select register (mbs). geti taddr function: taddr = t 5-0 , 0: 20h-7fh [mki mode] when table defined by tbr instruction is referenced pc 13-0 (taddr) 5-0 + (taddr+1) when table defined by tcall instruction is referenced (sp 1) pc 7-4 , (sp 2) pc 3-0 (sp 3) mbe, rbe, pc 13,12 (sp 4) pc 11-8 pc 13-0 (taddr) 5-0 + (taddr+1) sp sp 4 when table defined by instruction other than tbr and tcall is referenced executes instruction with (taddr) (taddr+1) as op code i/ii
chapter 11 instruction set 399 user s manual u10201ej2v4um00 [mkii mode] when table defined by tbr instruction is referenced note pc 13-0 (taddr) 5-0 + (taddr+1) when table defined by tcall instruction is referenced note (sp 2) , , mbe, rbe (sp 3) pc 7-4 , (sp 4) pc 3-0 (sp 5) 0, 0, pc 13, pc 14, (sp 6) pc 11-8 pc 13-0 (taddr) 5-0 + (taddr+1), sp sp 6 when table defined by instruction other than tbr and tcall is referenced executes instruction with (taddr) (taddr+1) as op code note the address specified by the tbr and tcall instructions is limited to 0000h to 3fffh. references the 2-byte data at the program memory address specified by (taddr), (taddr+1) and executes it as an instruction. the area of the reference table consists of addresses 0020h through 007fh. data must be written to this area in advance. write the mnemonic of a 1-byte or 2-byte instruction as the data as is. when a 3-byte call instruction and 3-byte branch instruction is used, data is written by using an assembler pseudoinstruction (tcall or tbr). only an even address can be specified by taddr.
chapter 11 instruction set 400 user s manual u10201ej2v4um00 caution only the 2-machine cycle instruction can be set to the reference table as a 2-byte instruction (except the brcb and callf instructions). two 1-byte instructions can be set only in the following combinations: instruction of 1st byte instruction of 2nd byte mov a, @hl incs l mov @hl, a decs l xch a, @hl incs h decs h incs hl mov a, @de incs e xch a, @de decs e incs d decs d incs de mov a, @dl incs l xch a, @dl decs l incs d decs d the contents of the pc are not incremented while the geti instruction is executed. therefore, after the reference instruction has been executed, processing continues from the address next to that of the geti instruction. if the instruction preceding the geti instruction has a skip function, the geti instruction is skipped in the same manner as the other 1-byte instructions. if the instruction referenced by the geti instruction has a skip function, the instruction that follows the geti instruction is skipped. if an instruction having a string effect is referenced by the geti instruction, it is executed as follows: if the instruction preceding the geti instruction has the string effect of the same group as the referenced instruction, the string effect is lost and the referenced instruction is not skipped when geti is executed. if the instruction next to geti has the string effect of the same group as the referenced instruction, the string effect by the referenced instruction is valid, and the instruction following that instruction is skipped.
chapter 11 instruction set 401 user s manual u10201ej2v4um00 application example mov hl, #00h mov xa, #ffh call sub1 br sub2 org 20h hl00: mov hl, #00h xaff: mov xa, #ffh csub1: tcall sub1 bsub2: tbr sub2 geti hl00 ; mov hl, #00h geti bsub2 ; br sub2 geti csub1 ; call sub1 geti xaff ; mov xa, #ffh replaced by geti ......... ......... ......... .........
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403 user? manual u10201ej2v4um00 appendix a functions of pd75336, 753036, and 75p3036 (1/2) item pd75336 pd753036 pd75p3036 program memory mask rom mask rom prom note 0000h-3f7fh 0000h-3fffh 0000h-3fffh (16256 8 bits) (16384 8 bits) (16384 8 bits) data memory 000h-2ffh (768 4 bits) cpu 75x high-end 75xl cpu with main system 0.95, 1.91, 3.81, 15.3 s 0.95, 1.91, 3.81, 15,3 s (at 4.19 mhz) clock (at 4.19 mhz) 0.67, 1.33, 2.67, 10.7 s (at 6.0 mhz) with subsystem 122 s (at 32.768 khz) clock pin 48 p22/pcl p22/pcl/pto2 pins 50-53 p30-p33 p30/md0-p33/md3 pin 55 p81 p81/ti2 pin 69 ic v pp stack sbs register none sbs.3 = 1: selects mki mode sbs.3 = 0: selects mkii mode stack area 000h-0ffh n00h-nffh (n=0-2) stack operation of 2-byte stack mki mode: 2-byte stack subroutine call mkii mode: 3-byte stack instruction bra !addr1 cannot be used mki mode: cannot be used calla !addr1 mkii mode: can be used movt xa, @bcde can be used movt xa, @bcxa br bcde br bcxa call !addr 3 machine cycles mki mode: 3 machine cycles, mkii mode: 4 machine cycles callf !faddr 2 machine cycles mki mode: 2 machine cycles, mkii mode: 3 machine cycles timer instruc- tion execu- tion time pin connec- tion 4 channels basic interval timer: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel 5 channels basic interval timer/watchdog timer: 1 channel 8-bit timer/event counter: 3 channels (two channels can be used in combination as 16-bit timer/event counter.) watch timer: 1 channel note one-time prom and eprom instruction
appendix a functions of pd75336, 753036, and 75p3036 404 user? manual u10201ej2v4um00 (2/2) item pd75336 pd753036 pd75p3036 clock output (pcl) , 524, 262, 65.5 khz , 524, 262, 65.5 khz (main system clock at (main system clock at 4.19 mhz) 4.19 mhz) , 750, 375, 93.8 khz (main system clock at 6.0 mhz) buz output 2, 4, 32 khz 2, 4, 32 khz (main system clock at (main system clock at 4.19 mhz or subsystem clock: 4.19 mhz, subsystem clock 32.768 khz) at 32.768 khz) 2. 86, 5.72, 45.8 khz (main system clock at 6.0 mhz) serial interface three modes are supported 3-line serial i/o mode ... msb/lsb first selectable 2-line serial i/o mode sbi mode feedback resistor none provided cut flag (sos.0) suboscillator current none provided cut flag (sos.1) releasing standby by int0 impossible possible vectored interrupt external: 3, internal: 4 external: 3, internal: 5 supply voltage v dd =2.7 to 6.0 v v dd =1.8 to 5.5 v operating ambient temperature t a = ?0 to +85 c package 80-pin plastic tqfp (fine pitch) (12 12 mm) 80-pin plastic qfp (14 14 mm) 80-pin ceramic wqfn note ( pd75p3036 only) note under development sos reg- ister
405 user? manual u10201ej2v4um00 ~ appendix b development tools the following development tools are available to support development of systems using the pd753036. with the 75xl series, a relocatable assembler that can be used in common with any models in the series is used in combination with a device file dedicated to the model being used. language processor order code ibm pc/at tm or com- patible machine refer to os of ibm pc . order code os supply media pc-9800 series ms-dos 3.5"2hd s5a13df753036 ver.3.30 5"2hd s5a10df753036 ver.6.2 note 3.5" 2hc s7b13df753036 5"2hc s7b10df753036 ibm pc/at or compat- ible machine refer to os of ibm pc . note although ver.5.00 or above has a task swap function, this function cannot be used with this software. remark the operations of the assembler and device file are guaranteed only on the above host machines and os. ~ host machine ra75x relocatable assembler device file host machine os supply media pc-9800 series ms-dos 3.5"2hd s5a13ra75x ver.3.30 5"2hd s5a10ra75x ver.6.2 note 3.5" 2hc s7b13ra75x 5"2hc s7b10ra75x
appendix b development tools 406 user? manual u10201ej2v4um00 ~ prom writing tool pg-1500 this is a prom programmer that can program a built-in prom single-chip microcontroller in a stand-alone mode, or under control of a host computer when connected with an accessory board and an optional programmer adapter. it can also program typical proms from 256k-bit to 4m-bit models. pa-75p328gc prom programmer adapter dedicated to the pd75p3036gc and connected to the pg- 1500. pa-75p336gk prom programmer adapter dedicated to the pd75p3036gk and connected to the pg- 1500. pa-75p3036kk-t prom programmer adapter dedicated to the pd75p3036kk-t, and connected to the pg- 1500. pg-1500 controller connects the pg-1500 and a host machine with a parallel or serial interface to control the pg-1500 on the host machine. hardware order code ibm pc/at or compat- ible machine refer to os of ibm pc . software host machine os supply media pc-9800 series ms-dos 3.5"2hd s5a13pg1500 ver.3.30 5"2hd s5a10pg1500 ver.6.2 note 3.5" 2hc s7b13pg1500 5"2hc s7b10pg1500 note although ver.5.00 or above has a task swap function, this function cannot be used with this software. remark the operation of the pg-1500 controller is guaranteed only on the above host machines and os.
appendix b development tools 407 user? manual u10201ej2v4um00 ibm pc/at or compat- ible machine debugging tools as the debugging tools for the pd753036, in-circuit emulators (ie-75000-r and ie-75001-r) are available. the following table shows the system configuration of the in-circuit emulators. hardware ev-9200gc-80 order code software host machine refer to os of ibm pc . ~ os supply media pc-9800 series ms-dos 3.5"2hd s5a13ie75x ver.3.30 5"2hd s5a10ie75x ver.6.2 note2 3.5" 2hc s7b13ie75x 5"2hc s7b10ie75x notes 1. this is a maintenance part. 2. although ver.5.00 or above has a task swap function, this function cannot be used with this software. remark the operation of the ie control program is guaranteed only on the above host machines and os. ie-75000-r note1 the ie-75000-r is an in-circuit emulator that debugs the hardware and software of an application system using the 75x series or 75xl series. to develop the pd753036 subseries, use this in-circuit emulator with an optional emulation board ie-75300-r-em and emulation probe. the in-circuit emulator is connected with a host machine or prom programmer for efficient debugging. the ie-75000-r contains the emulation board ie-75000-r-em. ie-75001-r the ie-75001-r is an in-circuit emulator that debugs the hardware and software of an application system using the 75x series or 75xl series. to develop the pd753036 subseries, use this in-circuit emulator with an optional emulation board ie-75300-r-em and emulation probe. the in-circuit emulator is connected with a host machine or prom programmer to provide efficient debugging. ie-75300-r-em this is an emulation board to evaluate an application system using the pd753036 subseries. it is used with the ie-75000-r or ie-75001-r. ep-75336gc-r this is an emulation probe for the pd75336gc, 753036gc and 75p3036kk-t. it is connected to the ie-75000-r or ie-75001-r and ie-75300-r-em. an 8-pin conversion socket, ev-9200gc-80, that facilitates connection with the target system is also supplied. ep-75336gk-r this is an emulation probe for the pd75336gk and 753036gk. it is connected to the ie-75000-r or ie-75001-r and ie-75300-r-em. an 8-pin conversion socket, ev-9500gk-80, that facilitates connection with the target system is also supplied. jig used for removing the pd75p3036kk-t from the ev-9200gc-80. ie control program this program connects the ie-75000-r or ie-75001-r and a host machine with an rs-232c or centronics interface to control the ie-75000-r or ie-75001-r on the host machine. ev-9900 ev-9500gk-80
appendix b development tools 408 user? manual u10201ej2v4um00 os of ibm pc the following os is supported as the os for ibm pc. os version pc dos ver.5.02 to ver.6.3 j6.1/v note to j6.3/v note ms-dos ver.5.0 to ver.6.22 5.0/v note to 6.2/v note ibm dos tm j5.02/v note note only the english mode is supported. caution although ver.5.00 or above has a task swap function, this function cannot be used with this software.
appendix b development tools 409 user? manual u10201ej2v4um00 development tool configuration in-circuit emulator ie-75000-r or ie-75001-r emulation board ie-75300-r-em note 1 ie control program pg-1500 controller host machine pc-9800 series lbm pc/at [symbolic debugging possible] relocatable assembler + device file rs-232-c prom programmer pg-1500 + programmer adapter pa-75p328gc pa-75p336gk pa-75p3036kk-t emulation probe ep-75336gc-r ep-75336gk-r pd75p3036gc/gk/kk-t prom-contained model target system note 2 centronics l/f the in-circuit emulator is not provided with ie-75300-r-em (optional). ev-9200gc-80 ev-9500gk-80 notes 1. 2.
appendix b development tools 410 user s manual u10201ej2v4um00 package drawings of conversion socket (ev-9200gc-80) and board fig. b-1 ev-9200gc-80 package drawings (reference) a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g0 item millimeters inches a b c d e f g h i j k l m o n p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059
appendix b development tools 411 user s manual u10201ej2v4um00 fig. b-2 recommended pattern of the ev-9200gc-80 board mounting (reference) a f d e c b g j k l h i 0.026 0.026 ev-9200gc-80-p1 item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 0.65 0.02 19=12.35 0.05 0.65 0.02 19=12.35 0.05 +0.001 _ 0.002 +0.003 _ 0.002 +0.001 _ 0.002 +0.003 _ 0.002 +0.003 _ 0.002 +0.003 _ 0.002 +0.001 _ 0.001 +0.001 _ 0.002 +0.001 _ 0.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution 0.748=0.486 0.748=0.486
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413 user? manual u10201ej2v4um00 appendix c ordering mask rom after your program has been developed, you can place an order for a mask rom using the following procedure: <1> reservation for mask rom ordering inform nec of when you intend to place an order for the mask rom. (nec? response may be delayed if we are not informed in advance.) <2> preparation of ordering media following three mediums are available for ordering mask rom. uv-eprom note 3.5-inch ibm format floppy disk (outside japan only) 5-inch ibm format floppy disk (outside japan only) note prepare three uv-eproms with the same contents. (for the product with mask option, write down the mask option data on the mask option information sheet.) <3> preparation of necessary documents fill out the following documents when ordering the mask rom: ?mask rom ordering sheet ?mask rom ordering check sheet ?mask option information sheet (necessary for product with mask option) <4> ordering submit the media prepared in <2> and documents prepared in <3> to nec by the order reservation date.
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415 user? manual u10201ej2v4um00 appendix d instruction index d.1 instruction index (by function) movt xa, @pcxa ... 348, 369 movt xa, @bcde ... 348, 369 movt xa, @bcxa ... 348, 370 [bit transfer instruction] mov1 cy, fmem.bit ... 348, 371 mov1 cy, pmem.@l ... 348, 371 mov1 cy, @h+mem.bit ... 348, 371 mov1 fmem.bit, cy ... 348, 371 mov1 pmem.@l, cy ... 348, 371 mov1 @h+mem.bit, cy ... 348, 371 [operation instruction] adds a, #n4 ... 348, 372 adds xa, #n8 ... 348, 372 adds a, @hl ... 348, 372 adds xa, rp' ... 348, 372 adds rp'1, xa ... 348, 372 addc a, @hl ... 348, 373 addc xa, rp' ... 348, 373 addc rp'1, xa ... 348, 373 subs a, @hl ... 348, 374 subs xa, rp' ... 348, 374 subs rp'1, xa ... 348, 374 subc a, @hl ... 348, 375 subc xa, rp' ... 348, 375 subc rp'1, xa ... 348, 375 and a, #n4 ... 348, 376 and a, @hl ... 348, 376 and xa, rp' ... 348, 376 and rp'1, xa ... 348, 376 or a, #n4 ... 348, 377 or a, @hl ... 348, 377 or xa, rp' ... 348, 377 [transfer instruction] mov a, #n4 ... 347, 360 mov reg1, #n4 ... 347, 360 mov xa, #n8 ... 347, 360 mov hl, #n8 ... 347, 361 mov rp2, #n8 ... 347, 361 mov a, @hl ... 347, 361 mov a, @hl+ ... 347, 361 mov a, @hl? ... 347, 361 mov a, @rpa1 ... 347, 362 mov xa, @hl ... 347, 362 mov @hl, a ... 347, 362 mov @hl, xa ... 347, 362 mov a, mem ... 347, 363 mov xa, mem ... 347, 363 mov mem, a ... 347, 363 mov mem, xa ... 347, 363 mov a, reg ... 347, 363 mov xa, rp' ... 347, 364 mov reg1, a ... 347, 364 mov rp'1, xa ... 347, 364 xch a, @hl ... 347, 365 xch a, @hl+ ... 347, 365 xch a, @hl? ... 347, 365 xch a, @rpa1 ... 347, 365 xch xa, @hl ... 347, 366 xch a, mem ... 347, 366 xch xa, mem ... 347, 366 xch a, reg1 ... 347, 366 xch xa, rp' ... 347, 366 [table reference instruction] movt xa, @pcde ... 348, 367
appendix d instruction index 416 user? manual u10201ej2v4um00 or rp'1, xa ... 348, 377 xor a, #n4 ... 348, 378 xor a, @hl ... 348, 378 xor xa, rp' ... 348, 378 xor rp'1, xa ... 348, 378 [accumulator instruction] rorc a ... 349, 379 not a ... 349, 379 [increment/decrement instruction] incs reg ... 349, 380 incs rp1 ... 349, 380 incs @hl ... 349, 380 incs mem ... 349, 380 decs reg ... 349, 380 decs rp' ... 349, 380 [compare instruction] ske reg, #n4 ... 349, 381 ske @hl, #n4 ... 349, 381 ske a, @hl ... 349, 381 ske xa, @hl ... 349, 381 ske a, reg ... 349, 381 ske xa, rp' ... 349, 381 [carry flag manipulation instruction] set1 cy ... 349, 382 clr1 cy ... 349, 382 skt cy ... 349, 382 not1 cy ... 349, 382 [memory bit manipulation instruction] set1 mem.bit ... 349, 383 set1 fmem.bit ... 349, 383 set1 pmem.@l ... 349, 383 set1 @h+mem.bit ... 349, 383 clr1 mem.bit ... 349, 383 clr1 fmem.bit ... 349, 383 clr1 pmem.@l ... 349, 383 clr1 @h+mem.bit ... 349, 383 skt mem.bit ... 349, 384 skt fmem.bit ... 349, 384 skt pmem.@l ... 349, 384 skt @h+mem.bit ... 349, 384 skf mem.bit ... 349, 384 skf fmem.bit ... 349, 384 skf pmem.@l ... 349, 384 skf @h+mem.bit ... 349, 384 sktclr fmem.bit ... 349, 385 sktclr pmem.@l ... 349, 385 sktclr @h+mem.bit ... 349, 385 and1 cy, fmem.bit ... 350, 385 and1 cy, pmem.@l ... 350, 385 and1 cy, @h+mem.bit ... 350, 385 or1 cy, fmem.bit ... 350, 385 or1 cy, pmem.@l ... 350, 385 or1 cy, @h+mem.bit ... 350, 385 xor1 cy, fmem.bit ... 350, 385 xor1 cy, pmem.@l ... 350, 385 xor1 cy, @h+mem.bit ... 350, 385 [branch instruction] br addr ... 350, 386 br addr1 ... 350, 386 br !addr ... 350, 386 br $addr ... 350, 386 br $addr1 ... 350, 387 br pcde ... 350, 388 br pcxa ... 350, 388 br bcde ... 350, 389 br bcxa ... 350, 389 bra !addr1 ... 350, 389 brcb !caddr ... 350, 387 [subroutine/stack control instruction] calla !addr1 ... 351, 390
appendix d instruction index 417 user? manual u10201ej2v4um00 call !addr ... 351, 390 callf !faddr ... 351, 391 tcall !addr ... 351, 391 ret ... 351, 392 rets ... 351, 392 reti ... 351, 393 push tp ... 352, 394 push bs ... 352, 394 pop rp ... 352, 394 pop bs ... 352, 394 [interrupt control instruction] ei ... 352, 395 ei ie ... 352, 395 di ... 352, 395 di ie ... 352, 395 [input/output instruction] in a, portn ... 352, 396 in xa, portn ... 352, 396 out portn, a ... 352, 396 out portn, xa ... 352, 396 [cpu control instruction] halt ... 352, 397 stop ... 352, 397 nop ... 352, 397 [special instruction] sel rbn ... 352, 398 sel mbn ... 352, 398 geti taddr ... 352, 398
appendix d instruction index 418 user? manual u10201ej2v4um00 d.2 instruction index (alphabetical order) [a] addc a, @hl ... 348, 373 addc rp'1, xa ... 348, 372 addc xa, rp' ... 348, 373 adds a, #n4 ... 348, 372 adds a, @hl ... 348, 372 adds rp'1, xa ... 348, 372 adds xa, rp' ... 348, 372 adds xa, #n8 ... 348, 372 and a, #n4 ... 348, 376 and a, @hl ... 348, 376 and rp'1, xa ... 348, 376 and xa, rp' ... 348, 376 and1 cy, fmem.bit ... 350, 385 and1 cy, pmem.@l ... 350, 385 and1 cy, @h+mem.bit ... 350, 385 [b] br addr ... 350, 386 br addr1 ... 350, 386 br bcde ... 350, 389 br bcxa ... 350, 389 br pcde ... 350, 388 br pcxa ... 350, 388 br !addr ... 350, 386 br $addr ... 350, 386 br $addr1 ... 350, 387 bra !addr1 ... 350, 386 brcb !caddr ... 350, 387 [c] call !addr ... 351, 390 calla !addr1 ... 351, 390 callf !faddr ... 351, 391 clr1 cy ... 349, 383 clr1 fmem.bit ... 349, 383 clr1 mem.bit ... 349, 383 clr1 pmem.@l ... 349, 383 clr1 @h+mem.bit ... 349, 383 [d] decs reg ... 349, 380 decs rp' ... 349, 380 di ... 352, 395 di ie ... 352, 395 [e] ei ... 352, 395 ei ie ... 352, 395 [g] geti taddr ... 352, 398 [h] halt ... 352, 397 [i] in a, portn ... 352, 396 in xa, portn ... 352, 396 incs mem ... 349, 380 incs reg ... 349, 380 incs rp1 ... 349, 380 incs @hl ... 349, 380 [m] mov a, mem ... 347, 363 mov a, reg ... 347, 363 mov a, #n4 ... 347, 360 mov a, @hl ... 347, 365 mov a, @hl+ ... 347, 365 mov a, @hl? ... 347, 365 mov a, @rpa1 ... 347, 362
appendix d instruction index 419 user? manual u10201ej2v4um00 mov hl, #n8 ... 347, 360 mov mem, a ... 347, 363 mov mem, xa ... 347, 363 mov reg1, a ... 347, 364 mov reg1, #n4 ... 347, 360 mov rp'1, xa ... 347, 364 mov rp2, #n8 ... 347, 361 mov xa, mem ... 347, 363 mov xa, rp' ... 347, 364 mov xa, #n8 ... 347, 360 mov xa, @hl ... 347, 362 mov @hl, a ... 347, 362 mov @hl, xa ... 347, 362 movt xa, @bcde ... 348, 369 movt xa, @bcxa ... 348, 370 movt xa, @pcde ... 348, 367 movt xa, @pcxa ... 348, 369 mov1 cy, fmem.bit ... 348, 371 mov1 cy, pmem.@l ... 348, 371 mov1 cy, @h+mem.bit ... 348, 371 mov1 fmem.bit, cy ... 348, 371 mov1 pmem.@l, cy ... 348, 371 mov1 @h+mem.bit, cy ... 348, 371 [h] nop ... 352, 397 not a ... 349, 379 not1 cy ... 349, 382 [o] or a, #n4 ... 348, 377 or a, @hl ... 348, 377 or rp'1, xa ... 348, 377 or xa, rp' ... 348, 377 or1 cy, fmem.bit ... 350, 385 or1 cy, pmem.@l ... 350, 385 or1 cy, @h+mem.bit ... 350, 385 out portn, a ... 352, 396 out portn, xa ... 352, 396 [p] pop bs ... 352, 394 pop rp ... 352, 394 push bs ... 352, 394 push rp ... 352, 394 [r] ret ... 351, 392 reti ... 351, 393 rets ... 351, 392 rorc a ... 349, 379 [s] sel mbn ... 352, 398 sel rbn ... 352, 398 set1 cy ... 349, 382 set1 fmem.bit ... 349, 383 set1 mem.bit ... 349, 383 set1 pmem.@l ... 349, 383 set1 @h+mem.bit ... 349, 383 ske a, reg ... 349, 381 ske a, @hl ... 349, 381 ske reg, #n4 ... 349, 381 ske xa, rp' ... 349, 381 ske xa, @hl ... 349, 381 ske @hl, #n4 ... 349, 381 skf fmem.bit ... 349, 384 skf mem.bit ... 349, 384 skf pmem.@l ... 349, 384 skf @h+mem.bit ... 349, 384 skt cy ... 349, 384 skt fmem.bit ... 349, 384 skt mem.bit ... 349, 384 skt pmem.@l ... 349, 384
appendix d instruction index 420 user? manual u10201ej2v4um00 skt @h+mem.bit ... 349, 384 sktclr fmem.bit ... 349, 385 sktclr pmem.@l ... 349, 385 sktclr @h+mem.bit ... 349, 385 stop ... 352, 397 subc a, @hl ... 348, 375 subc rp'1, xa ... 348, 375 subc xa, rp' ... 348, 375 subs a, @hl ... 348, 374 subs rp'1, xa ... 348, 374 subs xa, rp' ... 348, 374 [t] tbr addr ... 350, 389 tcall !addr ... 351, 391 [x] xch a, @rpa1 ... 347, 365 xch a, mem ... 347, 366 xch a, reg1 ... 347, 366 xch a, @hl ... 347, 365 xch a, @hl+ ... 347, 365 xch a, @hl? ... 347, 365 xch xa, @hl ... 347, 366 xch xa, mem ... 347, 366 xch xa, rp' ... 347, 366 xor a, #n4 ... 348, 378 xor a, @hl ... 348, 378 xor rp'1, xa ... 348, 378 xor xa, rp' ... 348, 378 xor1 cy, fmem.bit ... 350, 385 xor1 cy, pmem.@l ... 350, 385 xor1 cy, @h+mem.bit ... 350, 385
421 user? manual u10201ej2v4um00 appendix e hardware index [a] ackd ... 184 acke ... 184 ackt ... 184 aden ... 276 adm ... 276 [b] bp0-bp7 ... 72 bs ... 70 bsb0-bsb3 ... 282 bsye ... 184 bt ... 107 [c] clom ... 102 cmdd ... 184 cmdt ... 185 coi ... 180 csie ... 180 csim ... 181 cy ... 66 [e] eoc ... 276 [i] ie0 ... 287 ie1 ... 287 ie2 ... 310 ie4 ... 287 iebt ... 287 iecsi ... 287 iet0 ... 287 iet1 ... 287 iet2 ... 287 iew ... 310 im0 ... 293 im1 ... 293 im2 ... 313 ime ... 289 inta ... 47 intc ... 47 inte ... 47 intf ... 47 intg ... 47 inth ... 47 ips ... 288 irq0 ... 287 irq1 ... 287 irq2 ... 310 irq4 ... 287 irqbt ... 287 irqcsi ... 287 irqt0 ... 287 irqt1 ... 287 irqt2 ... 287 irqw ... 310 ist0, ist1 ... 294 [k] kr0-kr7 ... 311 [l] lcdc ... 250 lcdm ... 248
422 user? manual u10201ej2v4um00 [m] mbe ... 68 mbs ... 70 [n] nrz ... 125 nrzb ... 125 [p] pc ... 53 pcc ... 89 pmga, pmgb, pmgc ... 78 poga, pogb ... 85 port0-port8 ... 74 psw ... 66 [r] rbe ... 69 rbs ... 70 reld ... 184 relt ... 185 remc ... 125 [s] sa ... 277 sbic ... 183 sbs ... 52, 62 scc ... 91 sio ... 186 sk0-sk2 ... 67 soc ... 276 sos ... 98 sp ... 62 sva ... 187 [t] t0, t1, t2 ... 46 tgce ... 125 tm0, tm1, tm2 ... 120 tmod0, tmod1, tmod2 ... 46 tmod2h ... 45 toe0, toe1, toe2 ... 46 [w] wdtm ... 106 wm ... 114 wup ... 140 appendix e hardware index
423 user? manual u10201ej2v4um00 appendix f revision history the following table shows revision history of this manual. version contents applicable part 2nd pd753036 and pd75p3036 under development developed pd75p3036kk-t has been added. at n-ch open drain of ports 4 and 5, input voltage has been changed to 13 v from 12 v. when using external clock, xt2 has been changed to opposite phase input from leaving open. a note has been added indicating that when not using subsystem clock, supply voltage current can reduce by sos.0 = 1 at stop instruction execution. a figure of external circuit which determines output level of bp0 through bp7 has been added. a note has been added indicating that bra !addr1 and call !addr1 instructions can only be used in mkii mode. explanation of mask option has been added. the items of instruction function and application have been adjusted to that of instruction set and its operation. modification of the instruction list. the os supported has been upgraded. throughout chapter 2 pin function chapter 4 internal cpu function chapter 10 mask option chapter 11 instruction set appendix b development tools
